[llvm] r268641 - [Hexagon] Merge HexagonAlias.td into HexagonInstrAlias.td, NFC
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Thu May 5 10:10:37 PDT 2016
The build failures associated with this commit happen because the build
scripts need to be regenerated. Seems like they are not updated
correctly by cmake(?).
-Krzysztof
On 5/5/2016 11:19 AM, Krzysztof Parzyszek via llvm-commits wrote:
> Author: kparzysz
> Date: Thu May 5 11:19:36 2016
> New Revision: 268641
>
> URL: http://llvm.org/viewvc/llvm-project?rev=268641&view=rev
> Log:
> [Hexagon] Merge HexagonAlias.td into HexagonInstrAlias.td, NFC
>
> Removed:
> llvm/trunk/lib/Target/Hexagon/HexagonAlias.td
> Modified:
> llvm/trunk/lib/Target/Hexagon/Hexagon.td
> llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td
>
> Modified: llvm/trunk/lib/Target/Hexagon/Hexagon.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.td?rev=268641&r1=268640&r2=268641&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/Hexagon.td (original)
> +++ llvm/trunk/lib/Target/Hexagon/Hexagon.td Thu May 5 11:19:36 2016
> @@ -251,7 +251,6 @@ include "HexagonCallingConv.td"
> include "HexagonInstrInfo.td"
> include "HexagonIntrinsics.td"
> include "HexagonIntrinsicsDerived.td"
> -include "HexagonAlias.td"
>
> def HexagonInstrInfo : InstrInfo;
>
>
> Removed: llvm/trunk/lib/Target/Hexagon/HexagonAlias.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonAlias.td?rev=268640&view=auto
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonAlias.td (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonAlias.td (removed)
> @@ -1,94 +0,0 @@
> -//==- HexagonAlias.td - Hexagon Instruction Aliases ---------*- tablegen -*-==//
> -//
> -// The LLVM Compiler Infrastructure
> -//
> -// This file is distributed under the University of Illinois Open Source
> -// License. See LICENSE.TXT for details.
> -//
> -//===----------------------------------------------------------------------===//
> -
> -//===----------------------------------------------------------------------===//
> -// Hexagon Instruction Mappings
> -//===----------------------------------------------------------------------===//
> -
> -// V6_vassignp: Vector assign mapping.
> -let hasNewValue = 1, opNewValue = 0, isAsmParserOnly = 1 in
> -def HEXAGON_V6_vassignpair: CVI_VA_DV_Resource <
> - (outs VecDblRegs:$Vdd),
> - (ins VecDblRegs:$Vss),
> - "$Vdd = $Vss">;
> -
> -// maps Vd = #0 to Vd = vxor(Vd, Vd)
> -def : InstAlias<"$Vd = #0",
> - (V6_vxor VectorRegs:$Vd, VectorRegs:$Vd, VectorRegs:$Vd)>,
> - Requires<[HasV60T]>;
> -
> -// maps Vdd = #0 to Vdd = vsub(Vdd, Vdd)
> -def : InstAlias<"$Vdd = #0",
> - (V6_vsubw_dv VecDblRegs:$Vdd, VecDblRegs:$Vdd, VecDblRegs:$Vdd)>,
> - Requires<[HasV60T]>;
> -
> -// maps "$Qd = vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd = vcmp.eq($Vu.h, $Vv.h)"
> -def : InstAlias<"$Qd = vcmp.eq($Vu.uh, $Vv.uh)",
> - (V6_veqh VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> - Requires<[HasV60T]>;
> -
> -// maps "$Qd &= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd &= vcmp.eq($Vu.h, $Vv.h)"
> -def : InstAlias<"$Qd &= vcmp.eq($Vu.uh, $Vv.uh)",
> - (V6_veqh_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> - Requires<[HasV60T]>;
> -
> -// maps "$Qd |= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd |= vcmp.eq($Vu.h, $Vv.h)"
> -def : InstAlias<"$Qd |= vcmp.eq($Vu.uh, $Vv.uh)",
> - (V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> - Requires<[HasV60T]>;
> -
> -// maps "$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd ^= vcmp.eq($Vu.h, $Vv.h)"
> -def : InstAlias<"$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)",
> - (V6_veqh_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> - Requires<[HasV60T]>;
> -
> -// maps "$Qd = vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd = vcmp.eq($Vu.w, $Vv.w)"
> -def : InstAlias<"$Qd = vcmp.eq($Vu.uw, $Vv.uw)",
> - (V6_veqw VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> - Requires<[HasV60T]>;
> -
> -// maps "$Qd &= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd &= vcmp.eq($Vu.w, $Vv.w)"
> -def : InstAlias<"$Qd &= vcmp.eq($Vu.uw, $Vv.uw)",
> - (V6_veqw_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> - Requires<[HasV60T]>;
> -
> -// maps "$Qd |= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd |= vcmp.eq($Vu.w, $Vv.w)"
> -def : InstAlias<"$Qd |= vcmp.eq($Vu.uw, $Vv.uw)",
> - (V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> - Requires<[HasV60T]>;
> -
> -// maps "$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd ^= vcmp.eq($Vu.w, $Vv.w)"
> -def : InstAlias<"$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)",
> - (V6_veqw_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> - Requires<[HasV60T]>;
> -
> -// maps "$Qd = vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd = vcmp.eq($Vu.b, $Vv.b)"
> -def : InstAlias<"$Qd = vcmp.eq($Vu.ub, $Vv.ub)",
> - (V6_veqb VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> - Requires<[HasV60T]>;
> -
> -// maps "$Qd &= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd &= vcmp.eq($Vu.b, $Vv.b)"
> -def : InstAlias<"$Qd &= vcmp.eq($Vu.ub, $Vv.ub)",
> - (V6_veqb_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> - Requires<[HasV60T]>;
> -
> -// maps "$Qd |= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd |= vcmp.eq($Vu.b, $Vv.b)"
> -def : InstAlias<"$Qd |= vcmp.eq($Vu.ub, $Vv.ub)",
> - (V6_veqb_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> - Requires<[HasV60T]>;
> -
> -// maps "$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd ^= vcmp.eq($Vu.b, $Vv.b)"
> -def : InstAlias<"$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)",
> - (V6_veqb_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> - Requires<[HasV60T]>;
> -
> -// maps "$Rd.w = vextract($Vu, $Rs)" -> "$Rd = vextract($Vu, $Rs)"
> -def : InstAlias<"$Rd.w = vextract($Vu, $Rs)",
> - (V6_extractw IntRegs:$Rd, VectorRegs:$Vu, IntRegs:$Rs)>,
> - Requires<[HasV60T]>;
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td?rev=268641&r1=268640&r2=268641&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td Thu May 5 11:19:36 2016
> @@ -460,3 +460,84 @@ def : InstAlias<"$Pd=cmp.lt($Rs, $Rt)",
> def : InstAlias<"$Pd=cmp.ltu($Rs, $Rt)",
> (C2_cmpgtu PredRegs:$Pd, IntRegs:$Rt, IntRegs:$Rs), 0>;
>
> +// V6_vassignp: Vector assign mapping.
> +let hasNewValue = 1, opNewValue = 0, isAsmParserOnly = 1 in
> +def HEXAGON_V6_vassignpair: CVI_VA_DV_Resource <
> + (outs VecDblRegs:$Vdd),
> + (ins VecDblRegs:$Vss),
> + "$Vdd = $Vss">;
> +
> +// maps Vd = #0 to Vd = vxor(Vd, Vd)
> +def : InstAlias<"$Vd = #0",
> + (V6_vxor VectorRegs:$Vd, VectorRegs:$Vd, VectorRegs:$Vd)>,
> + Requires<[HasV60T]>;
> +
> +// maps Vdd = #0 to Vdd = vsub(Vdd, Vdd)
> +def : InstAlias<"$Vdd = #0",
> + (V6_vsubw_dv VecDblRegs:$Vdd, VecDblRegs:$Vdd, VecDblRegs:$Vdd)>,
> + Requires<[HasV60T]>;
> +
> +// maps "$Qd = vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd = vcmp.eq($Vu.h, $Vv.h)"
> +def : InstAlias<"$Qd = vcmp.eq($Vu.uh, $Vv.uh)",
> + (V6_veqh VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> + Requires<[HasV60T]>;
> +
> +// maps "$Qd &= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd &= vcmp.eq($Vu.h, $Vv.h)"
> +def : InstAlias<"$Qd &= vcmp.eq($Vu.uh, $Vv.uh)",
> + (V6_veqh_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> + Requires<[HasV60T]>;
> +
> +// maps "$Qd |= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd |= vcmp.eq($Vu.h, $Vv.h)"
> +def : InstAlias<"$Qd |= vcmp.eq($Vu.uh, $Vv.uh)",
> + (V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> + Requires<[HasV60T]>;
> +
> +// maps "$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd ^= vcmp.eq($Vu.h, $Vv.h)"
> +def : InstAlias<"$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)",
> + (V6_veqh_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> + Requires<[HasV60T]>;
> +
> +// maps "$Qd = vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd = vcmp.eq($Vu.w, $Vv.w)"
> +def : InstAlias<"$Qd = vcmp.eq($Vu.uw, $Vv.uw)",
> + (V6_veqw VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> + Requires<[HasV60T]>;
> +
> +// maps "$Qd &= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd &= vcmp.eq($Vu.w, $Vv.w)"
> +def : InstAlias<"$Qd &= vcmp.eq($Vu.uw, $Vv.uw)",
> + (V6_veqw_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> + Requires<[HasV60T]>;
> +
> +// maps "$Qd |= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd |= vcmp.eq($Vu.w, $Vv.w)"
> +def : InstAlias<"$Qd |= vcmp.eq($Vu.uw, $Vv.uw)",
> + (V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> + Requires<[HasV60T]>;
> +
> +// maps "$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd ^= vcmp.eq($Vu.w, $Vv.w)"
> +def : InstAlias<"$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)",
> + (V6_veqw_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> + Requires<[HasV60T]>;
> +
> +// maps "$Qd = vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd = vcmp.eq($Vu.b, $Vv.b)"
> +def : InstAlias<"$Qd = vcmp.eq($Vu.ub, $Vv.ub)",
> + (V6_veqb VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> + Requires<[HasV60T]>;
> +
> +// maps "$Qd &= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd &= vcmp.eq($Vu.b, $Vv.b)"
> +def : InstAlias<"$Qd &= vcmp.eq($Vu.ub, $Vv.ub)",
> + (V6_veqb_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> + Requires<[HasV60T]>;
> +
> +// maps "$Qd |= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd |= vcmp.eq($Vu.b, $Vv.b)"
> +def : InstAlias<"$Qd |= vcmp.eq($Vu.ub, $Vv.ub)",
> + (V6_veqb_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> + Requires<[HasV60T]>;
> +
> +// maps "$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd ^= vcmp.eq($Vu.b, $Vv.b)"
> +def : InstAlias<"$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)",
> + (V6_veqb_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
> + Requires<[HasV60T]>;
> +
> +// maps "$Rd.w = vextract($Vu, $Rs)" -> "$Rd = vextract($Vu, $Rs)"
> +def : InstAlias<"$Rd.w = vextract($Vu, $Rs)",
> + (V6_extractw IntRegs:$Rd, VectorRegs:$Vu, IntRegs:$Rs)>,
> + Requires<[HasV60T]>;
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
More information about the llvm-commits
mailing list