[PATCH] D19694: [LV] Only bail on interleaved accesses in predicated blocks

[silviu.baranga@arm.com via llvm-commits]

sbaranga added inline comments.

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Comment at: lib/Transforms/Vectorize/LoopVectorize.cpp:5056
@@ -5055,3 +5055,3 @@
   collectConstStridedAccesses(StrideAccesses, Strides);
 
   if (StrideAccesses.empty())
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With that change, analyzeInterleaving won't see all the loads/stores (as the predicated ones get skipped). Would this have any impact on the correctness of the analysis (it might be ok, but it's worth thinking about it).


http://reviews.llvm.org/D19694