[PATCH] D19826: More Details for Interprocedural Register Allocation project on GSoC 2016 page

[Vivek Pandya via llvm-commits]

vivekvpandya created this revision.
vivekvpandya added a reviewer: grosser.
vivekvpandya added a subscriber: llvm-commits.

This patch adds draft proposal link, blog URL and status reporting interval details for GSoC 2016 project named "Interprocedural Register Allocation". It also adds a status column to track to progress of project. It may help others  looking to move the previous year project forward.

http://reviews.llvm.org/D19826

Files:
  2016.html

Index: 2016.html
===================================================================
--- 2016.html
+++ 2016.html
@@ -11,55 +11,72 @@
 .tg th{font-family:Arial, sans-serif;font-size:14px;font-weight:normal;padding:10px 5px;border-style:solid;border-width:1px;overflow:hidden;word-break:normal;}
 .tg .tg-9hbo{font-weight:bold;vertical-align:top}
 .tg .tg-yw4l{vertical-align:top}
+.tg .tg-yw4la{color:#009ACD;font-weight:bold}
 </style>
 <table class="tg">
   <tr>
     <th class="tg-9hbo">Project Name<br></th>
+    <th class="tg-9hbo">Status</th>
     <th class="tg-9hbo">Student</th>
     <th class="tg-9hbo">Mentor</th>
   </tr>
   <tr>
     <td class="tg-yw4l">Better Alias Analysis By Default<br></td>
+    <td class="tg-yw4la">Active<br></td>
     <td class="tg-yw4l">Jia Chen<br></td>
     <td class="tg-yw4l">Hal Finkel / George Burgess IV<br></td>
   </tr>
   <tr>
     <td class="tg-yw4l">Capture Tracking Improvements<br></td>
+    <td class="tg-yw4la">Active<br></td>
     <td class="tg-yw4l">Scott Egerton<br></td>
     <td class="tg-yw4l">Nuno P. Lopes / Mehdi Amini</td>
   </tr>
   <tr>
     <td class="tg-yw4l">Enabling LLVM's self-hosted modules builds using libstdc++<br></td>
+    <td class="tg-yw4la">Active<br></td>
     <td class="tg-yw4l">Bianca-Cristina Cristescu<br></td>
     <td class="tg-yw4l">Vassil Vassilev<br></td>
   </tr>
   <tr>
     <td class="tg-yw4l">Finding and analysing copy-pasted code with clang<br></td>
+    <td class="tg-yw4la">Active<br></td>
     <td class="tg-yw4l">Raphael Isemann<br></td>
     <td class="tg-yw4l">Vassil Vassilev<br></td>
   </tr>
   <tr>
     <td class="tg-yw4l">Improvement of vectorization process in Polly<br></td>
+    <td class="tg-yw4la">Active<br></td>
     <td class="tg-yw4l">Roman Gareev<br></td>
     <td class="tg-yw4l">Tobias Grosser<br></td>
   </tr>
   <tr>
-    <td class="tg-yw4l">Interprocedural Register Allocation in LLVM<br></td>
-    <td class="tg-yw4l">Mehdi Amini<br></td>
-    <td class="tg-yw4l">Hal Finkel<br></td>
+    <td class="tg-yw4l">Interprocedural Register Allocation in LLVM<br>
+    	<a href="https://docs.google.com/document/d/1DrsaFJdtxV73Zpns2bEgjATLFcWuaYMPHuvt5THLeLk/edit?usp=sharing" target="_blank">Draft proposal 
+    	</a><br/>
+    	Reporting Interval : weekly </br>
+    	Personal website/blog : <a href="http://vivekvpandya.github.io/" target="_blank">vivekvpandya.github.io 
+    	</a><br/>
+    </td>
+    <td class="tg-yw4la">Active<br></td>
+    <td class="tg-yw4l">Vivek Pandya<br></td>
+    <td class="tg-yw4l">Mehdi Amini, Hal Finkel<br></td>
   </tr>
   <tr>
     <td class="tg-yw4l">Polly as an Analysis Pass in LLVM<br></td>
+    <td class="tg-yw4la">Active<br></td>
     <td class="tg-yw4l">Utpal Boral<br></td>
     <td class="tg-yw4l">Johannes Doerfert<br></td>
   </tr>
   <tr>
     <td class="tg-yw4l">SAFECode's Memory Policy Hardening<br></td>
+    <td class="tg-yw4la">Active<br></td>
     <td class="tg-yw4l">Zhengyang Liu<br></td>
     <td class="tg-yw4l">John Criswell<br></td>
   </tr>
   <tr>
     <td class="tg-yw4l">Enabiling Polyhedral Optimizations in Julia (funded by Julia)<br></td>
+    <td class="tg-yw4la">Active<br></td>
     <td class="tg-yw4l">Matthias Reisinger<br></td>
     <td class="tg-yw4l">Tobias Grosser, Tim Holy, Jameson<br></td>
   </tr>


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