[PATCH] D18890: [AArch64] add SSA Load Store optimization pass

[James Molloy via llvm-commits]

Hi,

So why aren't you doing this in codegen prepare or dag combine?

Cheers,

James

> On 30 Apr 2016, at 03:38, Jongwon Lee <jong.won.lee at samsung.com> wrote:
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> JongwonLee added a comment.
>
>> OK, but this functionality is useful for other backends too. It isn't ideal in the long term to put generic functionality needlessly in target-specific areas.
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>
>> If you're implementing this in the SLP vectorizer, why do you need to do it here as well?
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>
> The support of 64-bit SLP vectorization and this patch have some overlaps but not identical. Each has its own parts for optimization. And this patch can supplement SLP vectorization. For example, when loop unrolling is called after SLP vectorization, we lose the chance to pack 32-bit loads/stores unless SLP vectorization is called again. This patch can catch the chance that would happen due to the order of IR-level optimizations.
>
>
> http://reviews.llvm.org/D18890
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>
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