[llvm] r268064 - [PPC] Enable shuffling of VSX vectors

[Guozhi Wei via llvm-commits]

Author: carrot
Date: Fri Apr 29 12:00:54 2016
New Revision: 268064

URL: http://llvm.org/viewvc/llvm-project?rev=268064&view=rev
Log:
[PPC] Enable shuffling of VSX vectors

This patch fixes PR27078 by enabling shuffling of vectors if VSX is available.


Added:
    llvm/trunk/test/CodeGen/PowerPC/pr27078.ll
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=268064&r1=268063&r2=268064&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Fri Apr 29 12:00:54 2016
@@ -11940,10 +11940,8 @@ PPCTargetLowering::shouldExpandBuildVect
   if (VT == MVT::v2i64)
     return Subtarget.hasDirectMove(); // Don't need stack ops with direct moves
 
-  if (Subtarget.hasQPX()) {
-    if (VT == MVT::v4f32 || VT == MVT::v4f64 || VT == MVT::v4i1)
-      return true;
-  }
+  if (Subtarget.hasVSX() || Subtarget.hasQPX())
+    return true;
 
   return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
 }

Added: llvm/trunk/test/CodeGen/PowerPC/pr27078.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/pr27078.ll?rev=268064&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/pr27078.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/pr27078.ll Fri Apr 29 12:00:54 2016
@@ -0,0 +1,15 @@
+; RUN: llc -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=+vsx < %s | FileCheck %s
+
+define <4 x float> @bar(float* %p, float* %q) {
+  %1 = bitcast float* %p to <12 x float>*
+  %2 = bitcast float* %q to <12 x float>*
+  %3 = load <12 x float>, <12 x float>* %1, align 16
+  %4 = load <12 x float>, <12 x float>* %2, align 16
+  %5 = fsub <12 x float> %4, %3
+  %6 = shufflevector <12 x float> %5, <12 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
+  ret <4 x float>  %6
+
+; CHECK: vspltw
+; CHECK: vmrghw
+; CHECK: vsldoi
+}