[PATCH] D19713: [mips][microMIPS] Implement CFC*, CTC* and LDC* instructions

Hrvoje Varga via llvm-commits llvm-commits at lists.llvm.org
Fri Apr 29 01:27:21 PDT 2016


hvarga created this revision.
hvarga added reviewers: dsanders, sdardis, zoran.jovanovic, zbuljan.
hvarga added subscribers: llvm-commits, petarj, sdardis, dsanders.
Herald added a reviewer: vkalintiris.

This patch implements microMIPS32r6 CFC1, CFC2, CTC1, CTC2, LDC1 and LDC2 instructions.

There was a problem with the previous implementation of this patch (D18640) and because of that commit rL266861 was reverted.
After committing of the previous patch, test-suite failed with error message in the form of:

```
fatal error: error in backend: Cannot select: 0x3b52390: f64,ch = load<LD8[%43](tbaa=<0x3a0db98>)> 0x3af1180, 0x3b50300, undef:i32
```

There was a problem with selecting LDC1 instruction in LLVM backend.

For that reason, it is decided to revert commit rL266861 and make this patch which besides implementation of instructions and standard regression tests also includes CodeGen test (ldc1.ll).

http://reviews.llvm.org/D19713

Files:
  lib/Target/Mips/Disassembler/MipsDisassembler.cpp
  lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
  lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
  lib/Target/Mips/MicroMips32r6InstrFormats.td
  lib/Target/Mips/MicroMips32r6InstrInfo.td
  lib/Target/Mips/MicroMipsInstrFPU.td
  lib/Target/Mips/MicroMipsInstrInfo.td
  lib/Target/Mips/Mips32r6InstrInfo.td
  lib/Target/Mips/MipsInstrFPU.td
  lib/Target/Mips/MipsInstrInfo.td
  test/CodeGen/Mips/ldc1.ll
  test/MC/Disassembler/Mips/micromips32r6/valid.txt
  test/MC/Mips/micromips32r6/invalid-wrong-error.s
  test/MC/Mips/micromips32r6/valid.s
  test/MC/Mips/mips32r5/invalid.s
  test/MC/Mips/mips64r5/invalid.s
  test/MC/Mips/mips64r6/invalid.s

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