[llvm] r267927 - This reverts commit r265505.
Kit Barton via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 28 13:00:43 PDT 2016
Author: kbarton
Date: Thu Apr 28 15:00:42 2016
New Revision: 267927
URL: http://llvm.org/viewvc/llvm-project?rev=267927&view=rev
Log:
This reverts commit r265505.
Revert "[Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random number, set bool, and dfp test significance".
This patch has caused a functional regression in SPEC2k6 namd, and a performance regression in mesa-pipe.
Modified:
llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
llvm/trunk/lib/Target/PowerPC/README_P9.txt
llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s
llvm/trunk/test/MC/PowerPC/ppc64-encoding.s
Modified: llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp?rev=267927&r1=267926&r2=267927&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp Thu Apr 28 15:00:42 2016
@@ -528,10 +528,6 @@ public:
(Kind == Immediate && isInt<16>(getImm()) &&
(getImm() & 3) == 0); }
bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
- bool isD8RCRegNumber() const { return Kind == Immediate &&
- isUInt<5>(getImm()) &&
- // required even register id
- !(getImm() & 0x1); }
bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
bool isCCRegNumber() const { return (Kind == Expression
&& isUInt<3>(getExprCRVal())) ||
@@ -594,11 +590,6 @@ public:
Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
}
- void addRegD8RCOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
- }
-
void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
@@ -1229,19 +1220,6 @@ void PPCAsmParser::ProcessInstruction(MC
Inst = TmpInst;
break;
}
- // ISA3.0 Instructions:
- case PPC::SUBPCIS:
- case PPC::LNIA: {
- MCInst TmpInst;
- TmpInst.setOpcode(PPC::ADDPCIS);
- TmpInst.addOperand(Inst.getOperand(0));
- if (Opcode == PPC::SUBPCIS)
- addNegOperand(TmpInst, Inst.getOperand(1), getContext());
- else
- TmpInst.addOperand(MCOperand::createImm(0));
- Inst = TmpInst;
- break;
- }
}
}
Modified: llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp?rev=267927&r1=267926&r2=267927&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp Thu Apr 28 15:00:42 2016
@@ -242,12 +242,6 @@ static DecodeStatus DecodeF8RCRegisterCl
return decodeRegisterClass(Inst, RegNo, FRegs);
}
-static DecodeStatus DecodeD8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
- uint64_t Address,
- const void *Decoder) {
- return decodeRegisterClass(Inst, RegNo, FRegs);
-}
-
static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=267927&r1=267926&r2=267927&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Thu Apr 28 15:00:42 2016
@@ -1279,63 +1279,6 @@ def : Pat<(atomic_store_64 xaddr:$ptr,
let Predicates = [IsISA3_0] in {
-// [PO RT RA RB RC XO]
-class VA_RT5_RA5_RB5_RC5<bits<6> xo, string opc, InstrItinClass itin,
- list<dag> pattern>
- : VAForm_1a<xo, (outs g8rc:$rD), (ins g8rc:$rA, g8rc:$rB, g8rc:$rC),
- !strconcat(opc, " $rD, $rA, $rB, $rC"), itin, pattern>;
-
-// 64-bit Fixed-Point Multiply-Add High-DWord/High-DWord-Unsigned/Low-DWord
-def MADDHD : VA_RT5_RA5_RB5_RC5<48, "maddhd" , IIC_IntGeneral, []>;
-def MADDHDU : VA_RT5_RA5_RB5_RC5<49, "maddhdu", IIC_IntGeneral, []>;
-def MADDLD : VA_RT5_RA5_RB5_RC5<51, "maddld ", IIC_IntGeneral, []>;
-
-let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
-// Add PC Immediate Shifted
-def ADDPCIS8 : DX_RD5_IM16<19, 2, (outs g8rc:$rD), (ins s16imm:$IMM),
- "addpcis $rD, $IMM", IIC_IntSimple, []>;
-
-// Modulo {Signed/Unsigned}-Word
-def MODSW8 : X_RT5_RA5_RB5<779, "modsw", g8rc, IIC_IntDivW, []>;
-def MODUW8 : X_RT5_RA5_RB5<267, "moduw", g8rc, IIC_IntDivW, []>;
-}
-
-// Modulo {Signed/Unsigned}-DWord
-def MODSD : X_RT5_RA5_RB5<777, "modsd", g8rc, IIC_IntDivW, []>;
-def MODUD : X_RT5_RA5_RB5<265, "modud", g8rc, IIC_IntDivW, []>;
-
-// [PO RS RA sh XO sh Rc]
-multiclass XS_RS5_RA5_SH5r<bits<6> opcode, bits<9> xo, string opc,
- InstrItinClass itin, list<dag> pattern> {
- let BaseName = opc in {
- def NAME : XSForm_1<opcode, xo, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
- !strconcat(opc, " $rA, $rS, $SH"), itin, pattern>;
- let Defs = [CR0] in
- def o : XSForm_1<opcode, xo, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
- !strconcat(opc, ". $rA, $rS, $SH"), itin, pattern>,
- isDOT;
- }
-}
-
-// Deliver A Random Number
-def DARN : X_RD5_L2<31, 755, (outs g8rc:$rD), (ins u2imm:$L), "darn $rD, $L",
- IIC_IntGeneral, []>;
-
-// Extend-Sign Word and Shift Left Immediate
-defm EXTSWSLI : XS_RS5_RA5_SH5r<31, 445, "extswsli" , IIC_IntShift, []>;
-
-// Set Boolean
-def SETB : X_RD5_BFA3<31, 128, (outs g8rc:$rD), (ins u3imm:$BFA),
- "setb $rD, $BFA", IIC_IntGeneral, []>;
-
-// DFP Test Significance Immediate [Quad]
-def DTSTSFI : X_BF3_IM6_RS5<59, 675,
- (outs crbitrc:$BF), (ins u6imm:$UIM, f8rc:$FRB),
- "dtstsfi $BF, $UIM, $FRB", IIC_FPGeneral, []>;
-def DTSTSFIQ : X_BF3_IM6_RS5<63, 675,
- (outs crbitrc:$BF), (ins u6imm:$UIM, d8rc:$FRBp),
- "dtstsfiq $BF, $UIM, $FRBp", IIC_FPGeneral, []>;
-
class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,
InstrItinClass itin, list<dag> pattern>
: X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L),
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td?rev=267927&r1=267926&r2=267927&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td Thu Apr 28 15:00:42 2016
@@ -376,23 +376,6 @@ class DQ_RD6_RS5_DQ12<bits<6> opcode, bi
let Inst{29-31} = xo;
}
-// DX-Form: [PO RT d1 d0 XO d2]
-class DX_RD5_IM16<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
- InstrItinClass itin, list<dag> pattern>
- : I<opcode, OOL, IOL, asmstr, itin> {
- bits<5> RD;
- bits<16> IMM;
-
- let Pattern = pattern;
-
- let Inst{6-10} = RD;
- // IMM = d0 || d1 || d2
- let Inst{11-15} = IMM{5-1}; // d1
- let Inst{16-25} = IMM{15-6}; // d0
- let Inst{26-30} = xo;
- let Inst{31} = IMM{0}; // d2
-}
-
// 1.7.6 X-Form
class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
@@ -780,11 +763,6 @@ class XForm_htm3<bits<6> opcode, bits<10
}
// [PO RT RA RB XO /]
-class X_RT5_RA5_RB5<bits<10> xo, string opc, RegisterOperand type,
- InstrItinClass itin, list<dag> pattern>
- : XForm_base_r3xo<31, xo, (outs type:$rD), (ins type:$rA, type:$rB),
- !strconcat(opc, " $rD, $rA, $rB"), itin, pattern>;
-
class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> {
@@ -829,57 +807,6 @@ class X_RD5_XO5_RS5<bits<6> opcode, bits
let A = xo2;
}
-// [PO RT /// L /// XO /]
-class X_RD5_L2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
- InstrItinClass itin, list<dag> pattern>
- : I<opcode, OOL, IOL, asmstr, itin> {
- bits<5> RD;
- bits<2> L;
-
- let Pattern = pattern;
-
- let Inst{6-10} = RD;
- let Inst{11-13} = 0;
- let Inst{14-15} = L;
- let Inst{16-20} = 0;
- let Inst{21-30} = xo;
- let Inst{31} = 0;
-}
-
-// [PO RT BFA // /// XO /]
-class X_RD5_BFA3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
- InstrItinClass itin, list<dag> pattern>
- : I<opcode, OOL, IOL, asmstr, itin> {
- bits<5> RD;
- bits<3> BFA;
-
- let Pattern = pattern;
-
- let Inst{6-10} = RD;
- let Inst{11-13} = BFA;
- let Inst{14-20} = 0;
- let Inst{21-30} = xo;
- let Inst{31} = 0;
-}
-
-// [PO BF / UIM FRB XO /] or [PO BF / UIM FRBp XO /]
-class X_BF3_IM6_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
- string asmstr, InstrItinClass itin, list<dag> pattern>
- : I<opcode, OOL, IOL, asmstr, itin> {
- bits<3> BF;
- bits<6> UIM;
- bits<5> FRB;
-
- let Pattern = pattern;
-
- let Inst{6-8} = BF;
- let Inst{9} = 0;
- let Inst{10-15} = UIM;
- let Inst{16-20} = FRB;
- let Inst{21-30} = xo;
- let Inst{31} = 0;
-}
-
class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> {
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=267927&r1=267926&r2=267927&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Thu Apr 28 15:00:42 2016
@@ -423,12 +423,6 @@ def PPCRegF4RCAsmOperand : AsmOperandCla
def f4rc : RegisterOperand<F4RC> {
let ParserMatchClass = PPCRegF4RCAsmOperand;
}
-def PPCRegD8RCAsmOperand : AsmOperandClass {
- let Name = "RegD8RC"; let PredicateMethod = "isD8RCRegNumber";
-}
-def d8rc : RegisterOperand<D8RC> {
- let ParserMatchClass = PPCRegD8RCAsmOperand;
-}
def PPCRegVRRCAsmOperand : AsmOperandClass {
let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
}
@@ -4201,17 +4195,6 @@ def : Pat<(atomic_store_32 xaddr:$ptr, i
let Predicates = [IsISA3_0] in {
-// Add PC Immediate Shifted
-def ADDPCIS : DX_RD5_IM16<19, 2, (outs gprc:$rD), (ins s16imm:$IMM),
- "addpcis $rD, $IMM", IIC_IntSimple, []>;
-// Extended Mnemonics of ADDPCIS
-def SUBPCIS : PPCAsmPseudo<"subpcis $rD, $IMM", (ins gprc:$rD, s16imm:$IMM)>;
-def LNIA : PPCAsmPseudo<"lnia $rD", (ins gprc:$rD)>;
-
-// Modulo {Signed/Unsigned}-Word
-def MODSW : X_RT5_RA5_RB5<779, "modsw", gprc, IIC_IntDivW, []>;
-def MODUW : X_RT5_RA5_RB5<267, "moduw", gprc, IIC_IntDivW, []>;
-
// Copy-Paste Facility
// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to
// PASTE for naming consistency.
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td?rev=267927&r1=267926&r2=267927&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td Thu Apr 28 15:00:42 2016
@@ -18,8 +18,6 @@ def sub_un : SubRegIndex<1, 3>;
def sub_32 : SubRegIndex<32>;
def sub_64 : SubRegIndex<64>;
def sub_128 : SubRegIndex<128>;
-def subreg_l64 : SubRegIndex<64, 0>;
-def subreg_h64 : SubRegIndex<64, 64>;
}
@@ -51,14 +49,6 @@ class FPR<bits<5> num, string n> : PPCRe
let HWEncoding{4-0} = num;
}
-// DPR - One of the 16 128 bit floating-point registers
-// It is composed of FPR_even and FPR_odd
-class DPR<FPR even, FPR odd, string n> : PPCReg<n> {
- let HWEncoding = even.HWEncoding;
- let SubRegs = [even, odd];
- let SubRegIndices = [subreg_l64, subreg_h64];
-}
-
// QFPR - One of the 32 256-bit floating-point vector registers (used for QPX)
class QFPR<FPR SubReg, string n> : PPCReg<n> {
let HWEncoding = SubReg.HWEncoding;
@@ -126,13 +116,6 @@ foreach Index = 0-31 in {
DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;
}
-// 128-bit Paired Floating-point registers
-foreach Index = 0-15 in {
- def D#Index :
- DPR<!cast<FPR>("F"#!shl(Index, 1)),
- !cast<FPR>("F"#!add(!shl(Index, 1), 1)), "f"#!shl(Index, 1)>;
-}
-
// Floating-point vector subregisters (for VSX)
foreach Index = 0-31 in {
def VF#Index : VF<Index, "vs" # !add(Index, 32)>;
@@ -305,9 +288,6 @@ def F8RC : RegisterClass<"PPC", [f64], 6
(sequence "F%u", 31, 14))>;
def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
-def D8RC : RegisterClass<"PPC", [f128], 128, (add (sequence "D%u", 0, 6),
- (sequence "D%u", 15, 7))>;
-
def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v2i64,v1i128,v4f32], 128,
(add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
Modified: llvm/trunk/lib/Target/PowerPC/README_P9.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/README_P9.txt?rev=267927&r1=267926&r2=267927&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/README_P9.txt (original)
+++ llvm/trunk/lib/Target/PowerPC/README_P9.txt Thu Apr 28 15:00:42 2016
@@ -582,79 +582,6 @@ Move to CR from XER Extended (mcrxrx):
- Is there a use for this in LLVM?
Fixed Point Facility:
-- Add PC Immediate Shifted: addpcis subpcis
- . Thinking to use it on PC relative addressing mode?
-
-- 64-bit Fixed-Point Multiply-Add Low DWord: maddld
- . SDAG:
- (set i64:$rD, (add (mul $rA, $rB), $rC))
-
-- 64-bit Fixed-Point Multiply-Add High-DWord/High-DWord-Unsigned: maddhd maddhdu
- . Use intrinsic:
- (set i64:$rD, (int_ppc_maddhd i64:$rA, i64:$rB), i64:$rC))
- (set i64:$rD, (int_ppc_maddhdu i64:$rA, i64:$rB), i64:$rC))
-
-- Modulo {Signed/Unsigned}-{Word/DWord}: modsw moduw modsd modud
- . Map modulo signed to llvm srem, modulo unsigned to urem because each pair
- has same semantics, as follows:
-
- llvm srem:
- 1. This instruction returns the remainder of a division (where the result is
- either zero or has the same sign as the dividend, op1)
- 2. Undefined behavior:
- - <anything> % 0
- - Overflow: e.g. -2147483648 % -1
- In this case, the remainder doesnât actually overflow, but this rule
- lets srem be implemented using instructions that return both the result
- of the division and the remainder.
-
- Modulo Signed:
- 1. remainder = dividend - (quotient à divisor)
- where
- 0 ⤠remainder < |divisor|, if the dividend ⥠0
- -|divisor| < remainder ⤠0 , if the dividend < 0
-
- 2. Undefined behavior:
- - <anything> % 0
- - 0x8000_0000 % -1
-
- . SDAG:
- (set i32:$rD, (srem i32:$rA, i32:$rB)) // modsw
- (set i32:$rD, (urem i32:$rA, i32:$rB)) // moduw
- (set i64:$rD, (srem i64:$rA, i64:$rB)) // modsd
- (set i64:$rD, (urem i64:$rA, i64:$rB)) // modud
-
- . Note:
- The quotient is not supplied as a result in modulo word (32-bit)
- instructions
-
-- Deliver A Random Number: darn
- . Intrinsic?
- (set i64:$rD, (int_ppc_darn i2:$L))
-
- . Thinking for using it on c/c++ rand() implementation
-
-- Extend-Sign Word and Shift Left Immediate: extswsli extswsli.
- . SDAG:
- (set i64:$rA, shl((sext i32:$rS, i64), i6$SH))
-
-- Set Boolean: setb
- . Thinking to use it on:
-
- if (cond)
- return true;
- return false;
-
- . Need Intrinsic?
- (set i64:rD, (int_ppc_setb i3:$BFA))
-
-- DFP Test Significance Immediate [Quad]: dtstsfi dtstsfiq
- . Need write inline assembly to test paired floating point register
- allocation for dtstsfiq
-
- . Intrinsics:
- (set i1:$BF, (int_ppc_dtstsfi i6:$UIM, f64:$FRB))
- (set i1:$BF, (int_ppc_dtstsfiq i6:$UIM, f128:$FRBp))
- Copy-Paste Facility: copy copy_first cp_abort paste paste. paste_last
. Use instrinstics:
Modified: llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt?rev=267927&r1=267926&r2=267927&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt (original)
+++ llvm/trunk/test/MC/Disassembler/PowerPC/ppc64-encoding.txt Thu Apr 28 15:00:42 2016
@@ -688,50 +688,6 @@
# CHECK: mfsrin 10, 12
0x7d 0x40 0x65 0x26
-# ISA3.0 Instructions:
-
-# CHECK: addpcis 1, -12345
-0x4c 0x23 0xcf 0xc5
-
-# CHECK: maddhd 30, 27, 7, 2
-0x13 0xdb 0x38 0xb0
-
-# CHECK: maddhdu 15, 12, 1, 3
-0x11 0xec 0x08 0xf1
-
-# CHECK: maddld 13, 10, 6, 4
-0x11 0xaa 0x31 0x33
-
-# CHECK: modsw 2, 3, 4
-0x7c 0x43 0x26 0x16
-
-# CHECK: moduw 3, 7, 5
-0x7c 0x67 0x2a 0x16
-
-# CHECK: modsd 10, 13, 14
-0x7d 0x4d 0x76 0x12
-
-# CHECK: modud 21, 15, 27
-0x7e 0xaf 0xda 0x12
-
-# CHECK: darn 31, 2
-0x7f 0xe2 0x05 0xe6
-
-# CHECK: extswsli 15, 18, 63
-0x7e 0x4f 0xfe 0xf6
-
-# CHECK: extswsli. 11, 27, 31
-0x7f 0x6b 0xfe 0xf5
-
-# CHECK: setb 2, 7
-0x7c 0x5c 0x01 0x00
-
-# CHECK: dtstsfi 7, 63, 1
-0xef 0xbf 0x0d 0x46
-
-# CHECK: dtstsfiq 4, 63, 4
-0xfe 0x3f 0x25 0x46
-
# CHECK: copy 2, 19, 1
0x7c 0x22 0x9e 0x0c
Modified: llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s?rev=267927&r1=267926&r2=267927&view=diff
==============================================================================
--- llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s (original)
+++ llvm/trunk/test/MC/PowerPC/ppc64-encoding-ext.s Thu Apr 28 15:00:42 2016
@@ -3666,15 +3666,6 @@
# CHECK-LE: attn # encoding: [0x00,0x02,0x00,0x00]
attn
-# ISA3.0 Instructions:
-# Extended Mnemonics of ADDPCIS
-# CHECK-BE: addpcis 1, -12345 # encoding: [0x4c,0x23,0xcf,0xc5]
-# CHECK-LE: addpcis 1, -12345 # encoding: [0xc5,0xcf,0x23,0x4c]
- subpcis 1, 12345
-# CHECK-BE: addpcis 12, 0 # encoding: [0x4d,0x80,0x00,0x04]
-# CHECK-LE: addpcis 12, 0 # encoding: [0x04,0x00,0x80,0x4d]
- lnia 12
-
# Copy-Paste Facility (Extended Mnemonics):
# CHECK-BE: copy 2, 19, 0 # encoding: [0x7c,0x02,0x9e,0x0c]
# CHECK-LE: copy 2, 19, 0 # encoding: [0x0c,0x9e,0x02,0x7c]
Modified: llvm/trunk/test/MC/PowerPC/ppc64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-encoding.s?rev=267927&r1=267926&r2=267927&view=diff
==============================================================================
--- llvm/trunk/test/MC/PowerPC/ppc64-encoding.s (original)
+++ llvm/trunk/test/MC/PowerPC/ppc64-encoding.s Thu Apr 28 15:00:42 2016
@@ -873,64 +873,6 @@
# CHECK-LE: mfsrin 10, 12 # encoding: [0x26,0x65,0x40,0x7d]
mfsrin %r10,%r12
-# ISA3.0 Instructions:
-
-# Add PC Immediate Shifted
-# CHECK-BE: addpcis 1, -12345 # encoding: [0x4c,0x23,0xcf,0xc5]
-# CHECK-LE: addpcis 1, -12345 # encoding: [0xc5,0xcf,0x23,0x4c]
- addpcis 1, -12345
-
-# 64-bit Fixed-Point Multiply-Add High-DWord/High-DWord-Unsigned/Low-DWord
-# CHECK-BE: maddhd 30, 27, 7, 2 # encoding: [0x13,0xdb,0x38,0xb0]
-# CHECK-LE: maddhd 30, 27, 7, 2 # encoding: [0xb0,0x38,0xdb,0x13]
- maddhd 30, 27, 7, 2
-# CHECK-BE: maddhdu 15, 12, 1, 3 # encoding: [0x11,0xec,0x08,0xf1]
-# CHECK-LE: maddhdu 15, 12, 1, 3 # encoding: [0xf1,0x08,0xec,0x11]
- maddhdu 15, 12, 1, 3
-# CHECK-BE: maddld 13, 10, 6, 4 # encoding: [0x11,0xaa,0x31,0x33]
-# CHECK-LE: maddld 13, 10, 6, 4 # encoding: [0x33,0x31,0xaa,0x11]
- maddld 13, 10, 6, 4
-
-# Modulo {Signed/Unsigned}-{Word/DWord}
-# CHECK-BE: modsw 2, 3, 4 # encoding: [0x7c,0x43,0x26,0x16]
-# CHECK-LE: modsw 2, 3, 4 # encoding: [0x16,0x26,0x43,0x7c]
- modsw 2, 3, 4
-# CHECK-BE: moduw 3, 7, 5 # encoding: [0x7c,0x67,0x2a,0x16]
-# CHECK-LE: moduw 3, 7, 5 # encoding: [0x16,0x2a,0x67,0x7c]
- moduw 3, 7, 5
-# CHECK-BE: modsd 10, 13, 14 # encoding: [0x7d,0x4d,0x76,0x12]
-# CHECK-LE: modsd 10, 13, 14 # encoding: [0x12,0x76,0x4d,0x7d]
- modsd 10, 13, 14
-# CHECK-BE: modud 21, 15, 27 # encoding: [0x7e,0xaf,0xda,0x12]
-# CHECK-LE: modud 21, 15, 27 # encoding: [0x12,0xda,0xaf,0x7e]
- modud 21, 15, 27
-
-# Deliver A Random Number
-# CHECK-BE: darn 31, 2 # encoding: [0x7f,0xe2,0x05,0xe6]
-# CHECK-LE: darn 31, 2 # encoding: [0xe6,0x05,0xe2,0x7f]
- darn 31, 2
-
-# Extend-Sign Word and Shift Left Immediate
-# CHECK-BE: extswsli 15, 18, 63 # encoding: [0x7e,0x4f,0xfe,0xf6]
-# CHECK-LE: extswsli 15, 18, 63 # encoding: [0xf6,0xfe,0x4f,0x7e]
- extswsli 15, 18, 63
-# CHECK-BE: extswsli. 11, 27, 31 # encoding: [0x7f,0x6b,0xfe,0xf5]
-# CHECK-LE: extswsli. 11, 27, 31 # encoding: [0xf5,0xfe,0x6b,0x7f]
- extswsli. 11, 27, 31
-
-# Set Boolean
-# CHECK-BE: setb 2, 7 # encoding: [0x7c,0x5c,0x01,0x00]
-# CHECK-LE: setb 2, 7 # encoding: [0x00,0x01,0x5c,0x7c]
- setb 2, 7
-
-# DFP Test Significance Immediate [Quad]
-# CHECK-BE: dtstsfi 7, 63, 1 # encoding: [0xef,0xbf,0x0d,0x46]
-# CHECK-LE: dtstsfi 7, 63, 1 # encoding: [0x46,0x0d,0xbf,0xef]
- dtstsfi 7, 63, 1
-# CHECK-BE: dtstsfiq 4, 63, 4 # encoding: [0xfe,0x3f,0x25,0x46]
-# CHECK-LE: dtstsfiq 4, 63, 4 # encoding: [0x46,0x25,0x3f,0xfe]
- dtstsfiq 4, 63, 4
-
# Copy-Paste Facility
# CHECK-BE: copy 2, 19, 1 # encoding: [0x7c,0x22,0x9e,0x0c]
# CHECK-LE: copy 2, 19, 1 # encoding: [0x0c,0x9e,0x22,0x7c]
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