[llvm] r267849 - TargetRegisterInfo: Introduce reverseComposeSubRegIndexLaneMask()

[Matthias Braun via llvm-commits]

Author: matze
Date: Wed Apr 27 22:07:07 2016
New Revision: 267849

URL: http://llvm.org/viewvc/llvm-project?rev=267849&view=rev
Log:
TargetRegisterInfo: Introduce reverseComposeSubRegIndexLaneMask()

This function performs the reverse computation of
composeSubRegIndexLaneMask().

It will be used in the upcoming "DetectDeadLanes" pass.

Modified:
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
    llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=267849&r1=267848&r2=267849&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Wed Apr 27 22:07:07 2016
@@ -564,6 +564,20 @@ public:
     return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
   }
 
+  /// Transform a lanemask given for a virtual register to the corresponding
+  /// lanemask before using subregister with index \p IdxA.
+  /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a
+  /// valie lane mask (no invalid bits set) the following holds:
+  /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
+  /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
+  /// => X1 == Mask
+  LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA,
+                                                LaneBitmask LaneMask) const {
+    if (!IdxA)
+      return LaneMask;
+    return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
+  }
+
   /// Debugging helper: dump register in human readable form to dbgs() stream.
   static void dumpReg(unsigned Reg, unsigned SubRegIndex = 0,
                       const TargetRegisterInfo* TRI = nullptr);
@@ -580,6 +594,11 @@ protected:
     llvm_unreachable("Target has no sub-registers");
   }
 
+  virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned,
+                                                            LaneBitmask) const {
+    llvm_unreachable("Target has no sub-registers");
+  }
+
 public:
   /// Find a common super-register class if it exists.
   ///

Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=267849&r1=267848&r2=267849&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Wed Apr 27 22:07:07 2016
@@ -728,15 +728,11 @@ RegisterInfoEmitter::emitComposeSubRegIn
     SubReg2SequenceIndexMap.push_back(Found);
   }
 
-  OS << "unsigned " << ClName
-     << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, unsigned LaneMask)"
-        " const {\n";
-
   OS << "  struct MaskRolOp {\n"
         "    unsigned Mask;\n"
         "    uint8_t  RotateLeft;\n"
         "  };\n"
-        "  static const MaskRolOp Seqs[] = {\n";
+        "  static const MaskRolOp LaneMaskComposeSequences[] = {\n";
   unsigned Idx = 0;
   for (size_t s = 0, se = Sequences.size(); s != se; ++s) {
     OS << "    ";
@@ -756,24 +752,43 @@ RegisterInfoEmitter::emitComposeSubRegIn
   for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) {
     OS << "    ";
     unsigned Idx = SubReg2SequenceIndexMap[i];
-    OS << format("&Seqs[%u]", Idx);
+    OS << format("&LaneMaskComposeSequences[%u]", Idx);
     if (i+1 != e)
       OS << ",";
     OS << " // to " << SubRegIndices[i].getName() << "\n";
   }
   OS << "  };\n\n";
 
-  OS << "  --IdxA; assert(IdxA < " << SubRegIndices.size()
+  OS << "LaneBitmask " << ClName
+     << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)"
+        " const {\n"
+        "  --IdxA; assert(IdxA < " << SubRegIndices.size()
      << " && \"Subregister index out of bounds\");\n"
-        "  unsigned Result = 0;\n"
+        "  LaneBitmask Result = 0;\n"
         "  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask != 0; ++Ops)"
         " {\n"
-        "    unsigned Masked = LaneMask & Ops->Mask;\n"
+        "    LaneBitmask Masked = LaneMask & Ops->Mask;\n"
         "    Result |= (Masked << Ops->RotateLeft) & 0xFFFFFFFF;\n"
         "    Result |= (Masked >> ((32 - Ops->RotateLeft) & 0x1F));\n"
         "  }\n"
         "  return Result;\n"
-        "}\n";
+        "}\n\n";
+
+  OS << "LaneBitmask " << ClName
+     << "::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, "
+        " LaneBitmask LaneMask) const {\n"
+        "  LaneMask &= getSubRegIndexLaneMask(IdxA);\n"
+        "  --IdxA; assert(IdxA < " << SubRegIndices.size()
+     << " && \"Subregister index out of bounds\");\n"
+        "  LaneBitmask Result = 0;\n"
+        "  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask != 0; ++Ops)"
+        " {\n"
+        "    LaneBitmask Rotated = (LaneMask >> Ops->RotateLeft) |\n"
+        "                          ((LaneMask << ((32 - Ops->RotateLeft) & 0x1F)) & 0xFFFFFFFF);\n"
+        "    Result |= Rotated & Ops->Mask;\n"
+        "  }\n"
+        "  return Result;\n"
+        "}\n\n";
 }
 
 //
@@ -1078,8 +1093,10 @@ RegisterInfoEmitter::runTargetHeader(raw
   if (!RegBank.getSubRegIndices().empty()) {
     OS << "  unsigned composeSubRegIndicesImpl"
        << "(unsigned, unsigned) const override;\n"
-       << "  unsigned composeSubRegIndexLaneMaskImpl"
-       << "(unsigned, unsigned) const override;\n"
+       << "  LaneBitmask composeSubRegIndexLaneMaskImpl"
+       << "(unsigned, LaneBitmask) const override;\n"
+       << "  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl"
+       << "(unsigned, LaneBitmask) const override;\n"
        << "  const TargetRegisterClass *getSubClassWithSubReg"
        << "(const TargetRegisterClass*, unsigned) const override;\n";
   }