[llvm] r260806 - LiveIntervalAnalysis: Remove LiveVariables requirement
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 27 16:35:02 PDT 2016
ping2!
I'd really like to re-apply this patch! I don't want to deliberately break the bots, but I don't see any problem with my change and I still have no way to investigate/reproduce the powerpc issue here...
- Matthias
> On Mar 8, 2016, at 11:42 AM, Matthias Braun <matze at braunis.de> wrote:
>
> ping! +CC some PowerPC folks, any idea how I can go about debugging a problem on a power PC stage2 bot?
>
> - Matthias
>
>> On Mar 2, 2016, at 11:18 AM, Matthias Braun <mbraun at apple.com> wrote:
>>
>> Hi,
>>
>> is there any update on this? I'd like to put my commit back eventually but need a way to debug this stage 2 failure on ppc...
>>
>> - Matthias
>>
>>> On Feb 17, 2016, at 4:35 PM, Matthias Braun via llvm-commits <llvm-commits at lists.llvm.org> wrote:
>>>
>>> Thinking about this I have no idea how to go about debugging this. So this looks like a miscompile on stage1 which means one of the many llvm files is compiled incorrectly. To check which I would need to replicate this build which I cannot (no SDK etc.).
>>>
>>> So to move ahead could you try to llvm twice with my patch enabled and disabled, see which .o files changed if you build with the same source and destination paths you should hopefully only see cases where the actual instructions changed. You could then send me a preprocessed input and the commandline you use to build the file for one of the files that changed so I have something to work on?
>>>
>>> - Matthias
>>>
>>>> On Feb 17, 2016, at 4:12 PM, Matthias Braun <matze at braunis.de> wrote:
>>>>
>>>> Hi Bill,
>>>>
>>>> thanks for the report, I must have missed the original buildbot mail inside the errors of a bunch of other targets which were just affected by a little typo. Interestingly this seems to be the only target that broke like that. Anyway I will investigate and if I can't fix it today I will revert the changes (they are only there to enable a unittest I wrote).
>>>>
>>>> - Matthias
>>>>
>>>>> On Feb 17, 2016, at 3:17 PM, Bill Seurer <seurer at linux.vnet.ibm.com> wrote:
>>>>>
>>>>> Hi. This revision is causing failures on the powerpc64 llvm buildbots that do multi-stage builds. 4 of them fail when doing the stage2 build. I can duplicate the failure by doing a stage2 build by hand.
>>>>>
>>>>> I took the changes in r260806 out by hand from the latest source and then everything works OK.
>>>>>
>>>>> Example buildbot failures:
>>>>> http://lab.llvm.org:8011/builders/clang-ppc64le-linux-multistage/builds/286
>>>>> http://lab.llvm.org:8011/builders/clang-ppc64be-linux-multistage/builds/730
>>>>>
>>>>>
>>>>> The basic error is this:
>>>>>
>>>>> *** Bad machine code: PHI operand is not in the CFG ***
>>>>> - function: _ZL19simplifyX86immShiftRKN4llvm13IntrinsicInstERNS_9IRBuilderILb1ENS_12TargetFolderENS_21InstCombineIRInserterEEE
>>>>> - basic block: BB#116 cleanup85 (0x10009352f30)
>>>>> - instruction: %vreg64<def> = PHI
>>>>> - operand 4: <BB#123>
>>>>> fatal error: error in backend: Found 1 machine code errors.
>>>>> clang-3.8: error: clang frontend command failed with exit code 70 (use -v to see invocation)
>>>>>
>>>>>
>>>>>
>>>>> Full output from the failing compilation:
>>>>>
>>>>> [ 15%] Building CXX object lib/Transforms/InstCombine/CMakeFiles/LLVMInstCombine.dir/InstCombineCalls.cpp.o
>>>>> cd /home/seurer/llvm/build/llvm-test/lib/Transforms/InstCombine && /home/seurer/llvm/install/llvm-test/bin/clang++ -DGTEST_HAS_RTTI=0 -D_DEBUG -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -fPIC -fvisibility-inlines-hidden -Wall -W -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wcovered-switch-default -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -std=c++11 -ffunction-sections -fdata-sections -O3 -I/home/seurer/llvm/build/llvm-test/lib/Transforms/InstCombine -I/home/seurer/llvm/llvm-test/lib/Transforms/InstCombine -I/home/seurer/llvm/build/llvm-test/include -I/home/seurer/llvm/llvm-test/include -UNDEBUG -fno-exceptions -fno-rtti -o CMakeFiles/LLVMInstCombine.dir/InstCombineCalls.cpp.o -c /home/seurer/llvm/llvm-test/lib/Transforms/InstCombine/InstCombineCalls.cpp
>>>>>
>>>>> # Machine code for function _ZL19simplifyX86immShiftRKN4llvm13IntrinsicInstERNS_9IRBuilderILb1ENS_12TargetFolderENS_21InstCombineIRInserterEEE: SSA
>>>>> Frame Objects:
>>>>> fi#0: size=16, align=8, at location [SP]
>>>>> fi#1: size=16, align=8, at location [SP]
>>>>> fi#2: size=16, align=8, at location [SP]
>>>>> fi#3: size=16, align=8, at location [SP]
>>>>> fi#4: size=24, align=8, at location [SP]
>>>>> fi#5: size=24, align=8, at location [SP]
>>>>> fi#6: size=24, align=8, at location [SP]
>>>>> fi#7: size=24, align=8, at location [SP]
>>>>> Function Live Ins: %X3 in %vreg65, %X4 in %vreg66
>>>>>
>>>>> BB#0: derived from LLVM BB %entry
>>>>> Live Ins: %X3 %X4
>>>>> %vreg66<def> = COPY %X4; G8RC:%vreg66
>>>>> %vreg65<def> = COPY %X3; G8RC_and_G8RC_NOX0:%vreg65
>>>>> %vreg0<def> = LD -24, %vreg65; mem:LD8[%Val.i.i.i.i.i.i.i](tbaa=!3) G8RC_and_G8RC_NOX0:%vreg0,%vreg65
>>>>> %vreg67<def> = CMPLDI %vreg0, 0; CRRC:%vreg67 G8RC_and_G8RC_NOX0:%vreg0
>>>>> BCC 71, %vreg67, <BB#2>; CRRC:%vreg67
>>>>> B <BB#1>
>>>>> Successors according to CFG: BB#1(0x00000800 / 0x80000000 = 0.00%) BB#2(0x7ffff800 / 0x80000000 = 100.00%)
>>>>>
>>>>> BB#1: derived from LLVM BB %cond.false.i.i.i.i.i.i.i
>>>>> Predecessors according to CFG: BB#0
>>>>> %vreg521<def> = ADDIStocHA %X2, <ga:@.str.26>; G8RC_and_G8RC_NOX0:%vreg521
>>>>> %vreg522<def> = LI8 81; G8RC:%vreg522
>>>>> %vreg523<def> = ADDIStocHA %X2, <ga:@.str.25>; G8RC_and_G8RC_NOX0:%vreg523
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg524<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZN4llvm11isa_impl_clINS_8FunctionEPNS_5ValueEE4doitEPKS2_>; G8RC_and_G8RC_NOX0:%vreg524
>>>>> %vreg525<def> = ADDItocL %vreg521<kill>, <ga:@.str.26>; G8RC:%vreg525 G8RC_and_G8RC_NOX0:%vreg521
>>>>> %vreg526<def> = ADDItocL %vreg523<kill>, <ga:@.str.25>; G8RC:%vreg526 G8RC_and_G8RC_NOX0:%vreg523
>>>>> %vreg527<def> = ADDItocL %vreg524<kill>, <ga:@__PRETTY_FUNCTION__._ZN4llvm11isa_impl_clINS_8FunctionEPNS_5ValueEE4doitEPKS2_>; G8RC:%vreg527 G8RC_and_G8RC_NOX0:%vreg524
>>>>> %X3<def> = COPY %vreg525; G8RC:%vreg525
>>>>> %X4<def> = COPY %vreg526; G8RC:%vreg526
>>>>> %X5<def> = COPY %vreg522; G8RC:%vreg522
>>>>> %X6<def> = COPY %vreg527; G8RC:%vreg527
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#2: derived from LLVM BB %_ZNK4llvm13IntrinsicInst14getIntrinsicIDEv.exit
>>>>> Predecessors according to CFG: BB#0
>>>>> %vreg72<def> = LBZ 24, %vreg0; mem:LD1[%SubclassID.i.i.i.i.i.i.i.i.i](align=8)(tbaa=!20) GPRC:%vreg72 G8RC_and_G8RC_NOX0:%vreg0
>>>>> %vreg73<def> = CMPLWI %vreg72<kill>, 5; CRRC:%vreg73 GPRC:%vreg72
>>>>> %vreg68<def> = LI8 0; G8RC_and_G8RC_NOX0:%vreg68
>>>>> BCC 76, %vreg73, <BB#133>; CRRC:%vreg73
>>>>> Successors according to CFG: BB#132(?%) BB#133(?%)
>>>>>
>>>>> BB#132: derived from LLVM BB %_ZNK4llvm13IntrinsicInst14getIntrinsicIDEv.exit
>>>>> Predecessors according to CFG: BB#2
>>>>> Successors according to CFG: BB#133(?%)
>>>>>
>>>>> BB#133: derived from LLVM BB %_ZNK4llvm13IntrinsicInst14getIntrinsicIDEv.exit
>>>>> Predecessors according to CFG: BB#2 BB#132
>>>>> %vreg74<def> = PHI %vreg68, <BB#132>, %vreg0, <BB#2>; G8RC_and_G8RC_NOX0:%vreg74,%vreg68,%vreg0
>>>>> %vreg69<def> = CRUNSET; CRBITRC:%vreg69
>>>>> %vreg70<def> = LWZ 44, %vreg74<kill>; mem:LD4[%IntID.i.i](tbaa=!64) GPRC_and_GPRC_NOR0:%vreg70 G8RC_and_G8RC_NOX0:%vreg74
>>>>> %vreg71<def> = ADDI %vreg70, -4347; GPRC:%vreg71 GPRC_and_GPRC_NOR0:%vreg70
>>>>> %vreg75<def> = CMPLWI %vreg71, 21; CRRC:%vreg75 GPRC:%vreg71
>>>>> BCC 44, %vreg75<kill>, <BB#117>; CRRC:%vreg75
>>>>> B <BB#118>
>>>>> Successors according to CFG: BB#117(0x40000000 / 0x80000000 = 50.00%) BB#118(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#117: derived from LLVM BB %_ZNK4llvm13IntrinsicInst14getIntrinsicIDEv.exit
>>>>> Predecessors according to CFG: BB#120 BB#133
>>>>> %vreg88<def> = ADDI %vreg70, -6040; GPRC:%vreg88 GPRC_and_GPRC_NOR0:%vreg70
>>>>> %vreg89<def> = CMPLWI %vreg88, 15; CRRC:%vreg89 GPRC:%vreg88
>>>>> BCC 44, %vreg89<kill>, <BB#116>; CRRC:%vreg89
>>>>> B <BB#121>
>>>>> Successors according to CFG: BB#116(0x07878788 / 0x80000000 = 5.88%) BB#121(0x78787878 / 0x80000000 = 94.12%)
>>>>>
>>>>> BB#118: derived from LLVM BB %_ZNK4llvm13IntrinsicInst14getIntrinsicIDEv.exit
>>>>> Predecessors according to CFG: BB#133
>>>>> %vreg76<def> = LI 1; GPRC:%vreg76
>>>>> %vreg77<def> = SLW %vreg76, %vreg71; GPRC:%vreg77,%vreg76,%vreg71
>>>>> %vreg78<def> = RLWINM %vreg77, 0, 26, 31; GPRC:%vreg78,%vreg77
>>>>> %vreg79<def> = CMPLWI %vreg78<kill>, 0; CRRC:%vreg79 GPRC:%vreg78
>>>>> BCC 68, %vreg79<kill>, <BB#4>; CRRC:%vreg79
>>>>> Successors according to CFG: BB#4(0x2e8ba2e9 / 0x80000000 = 36.36%) BB#119(0x51745d17 / 0x80000000 = 63.64%)
>>>>>
>>>>> BB#119: derived from LLVM BB %_ZNK4llvm13IntrinsicInst14getIntrinsicIDEv.exit
>>>>> Predecessors according to CFG: BB#118
>>>>> %vreg82<def> = RLWINM %vreg77, 0, 10, 15; GPRC:%vreg82,%vreg77
>>>>> %vreg83<def> = CMPLWI %vreg82<kill>, 0; CRRC:%vreg83 GPRC:%vreg82
>>>>> BCC 68, %vreg83<kill>, <BB#3>; CRRC:%vreg83
>>>>> Successors according to CFG: BB#3(0x49249249 / 0x80000000 = 57.14%) BB#120(0x36db6db7 / 0x80000000 = 42.86%)
>>>>>
>>>>> BB#120: derived from LLVM BB %_ZNK4llvm13IntrinsicInst14getIntrinsicIDEv.exit
>>>>> Predecessors according to CFG: BB#119
>>>>> %vreg84<def> = LI 1; GPRC:%vreg84
>>>>> %vreg85<def> = SLW %vreg84<kill>, %vreg71; GPRC:%vreg85,%vreg84,%vreg71
>>>>> %vreg86<def> = RLWINM %vreg85<kill>, 0, 18, 21; GPRC:%vreg86,%vreg85
>>>>> %vreg87<def> = CMPLWI %vreg86<kill>, 0; CRRC:%vreg87 GPRC:%vreg86
>>>>> BCC 68, %vreg87<kill>, <BB#5>; CRRC:%vreg87
>>>>> B <BB#117>
>>>>> Successors according to CFG: BB#5(0x71c71c72 / 0x80000000 = 88.89%) BB#117(0x0e38e38e / 0x80000000 = 11.11%)
>>>>>
>>>>> BB#121: derived from LLVM BB %_ZNK4llvm13IntrinsicInst14getIntrinsicIDEv.exit
>>>>> Predecessors according to CFG: BB#117
>>>>> %vreg90<def> = LI 1; GPRC:%vreg90
>>>>> %vreg91<def> = SLW %vreg90, %vreg88; GPRC:%vreg91,%vreg90,%vreg88
>>>>> %vreg92<def> = RLWINM %vreg91, 0, 26, 31; GPRC:%vreg92,%vreg91
>>>>> %vreg93<def> = CMPLWI %vreg92<kill>, 0; CRRC:%vreg93 GPRC:%vreg92
>>>>> BCC 68, %vreg93<kill>, <BB#4>; CRRC:%vreg93
>>>>> Successors according to CFG: BB#4(0x30000000 / 0x80000000 = 37.50%) BB#122(0x50000000 / 0x80000000 = 62.50%)
>>>>>
>>>>> BB#122: derived from LLVM BB %_ZNK4llvm13IntrinsicInst14getIntrinsicIDEv.exit
>>>>> Predecessors according to CFG: BB#121
>>>>> %vreg96<def> = RLWINM %vreg91, 0, 16, 21; GPRC:%vreg96,%vreg91
>>>>> %vreg97<def> = CMPLWI %vreg96<kill>, 0; CRRC:%vreg97 GPRC:%vreg96
>>>>> BCC 68, %vreg97<kill>, <BB#3>; CRRC:%vreg97
>>>>> B <BB#5>
>>>>> Successors according to CFG: BB#3(0x4ccccccd / 0x80000000 = 60.00%) BB#5(0x33333333 / 0x80000000 = 40.00%)
>>>>>
>>>>> BB#123: derived from LLVM BB %_ZNK4llvm13IntrinsicInst14getIntrinsicIDEv.exit
>>>>>
>>>>> BB#3: derived from LLVM BB %sw.bb1
>>>>> Predecessors according to CFG: BB#119 BB#122
>>>>> %vreg100<def> = CRSET; CRBITRC:%vreg100
>>>>> B <BB#5>
>>>>> Successors according to CFG: BB#5(?%)
>>>>>
>>>>> BB#4: derived from LLVM BB %sw.bb2
>>>>> Predecessors according to CFG: BB#118 BB#121
>>>>> %vreg98<def> = CRSET; CRBITRC:%vreg98
>>>>> Successors according to CFG: BB#5(?%)
>>>>>
>>>>> BB#5: derived from LLVM BB %cond.end
>>>>> Predecessors according to CFG: BB#120 BB#122 BB#4 BB#3
>>>>> %vreg1<def> = PHI %vreg69, <BB#120>, %vreg69, <BB#122>, %vreg98, <BB#4>, %vreg69, <BB#3>; CRBITRC:%vreg1,%vreg69,%vreg69,%vreg98,%vreg69
>>>>> %vreg2<def> = PHI %vreg69, <BB#120>, %vreg69, <BB#122>, %vreg98, <BB#4>, %vreg100, <BB#3>; CRBITRC:%vreg2,%vreg69,%vreg69,%vreg98,%vreg100
>>>>> %vreg101<def> = LWZ 28, %vreg65; mem:LD4[%NumUserOperands.i.i.i.i.i] GPRC:%vreg101 G8RC_and_G8RC_NOX0:%vreg65
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg65; G8RC_and_G8RC_NOX0:%vreg65
>>>>> BL8_NOP <ga:@_ZNK4llvm17OperandBundleUserINS_8CallInstEPNS_3UseEE25getNumTotalBundleOperandsEv>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X2<imp-use>, %R1<imp-def>, %X3<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg102<def> = COPY %X3; G8RC:%vreg102
>>>>> %vreg103<def> = COPY %vreg102:sub_32; GPRC:%vreg103 G8RC:%vreg102
>>>>> %vreg104<def> = NOR %vreg103, %vreg103; GPRC:%vreg104,%vreg103,%vreg103
>>>>> %vreg105<def> = RLWINM %vreg101, 28, 4, 31; GPRC:%vreg105,%vreg101
>>>>> %vreg106<def> = ADD4 %vreg105<kill>, %vreg104<kill>; GPRC:%vreg106,%vreg105,%vreg104
>>>>> %vreg107<def> = CMPLWI %vreg106<kill>, 1; CRRC:%vreg107 GPRC:%vreg106
>>>>> BCC 47, %vreg107<kill>, <BB#7>; CRRC:%vreg107
>>>>> B <BB#6>
>>>>> Successors according to CFG: BB#7(0x7ffff800 / 0x80000000 = 100.00%) BB#6(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#6: derived from LLVM BB %cond.false.i
>>>>> Predecessors according to CFG: BB#5
>>>>> %vreg108<def> = ADDIStocHA %X2, <ga:@.str.22>; G8RC_and_G8RC_NOX0:%vreg108
>>>>> %vreg109<def> = LI8 1543; G8RC:%vreg109
>>>>> %vreg110<def> = ADDIStocHA %X2, <ga:@.str.23>; G8RC_and_G8RC_NOX0:%vreg110
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg111<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZNK4llvm8CallInst13getArgOperandEj>; G8RC_and_G8RC_NOX0:%vreg111
>>>>> %vreg112<def> = ADDItocL %vreg108<kill>, <ga:@.str.22>; G8RC:%vreg112 G8RC_and_G8RC_NOX0:%vreg108
>>>>> %vreg113<def> = ADDItocL %vreg110<kill>, <ga:@.str.23>; G8RC:%vreg113 G8RC_and_G8RC_NOX0:%vreg110
>>>>> %vreg114<def> = ADDItocL %vreg111<kill>, <ga:@__PRETTY_FUNCTION__._ZNK4llvm8CallInst13getArgOperandEj>; G8RC:%vreg114 G8RC_and_G8RC_NOX0:%vreg111
>>>>> %X3<def> = COPY %vreg112; G8RC:%vreg112
>>>>> %X4<def> = COPY %vreg113; G8RC:%vreg113
>>>>> %X5<def> = COPY %vreg109; G8RC:%vreg109
>>>>> %X6<def> = COPY %vreg114; G8RC:%vreg114
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#7: derived from LLVM BB %cond.end.i
>>>>> Predecessors according to CFG: BB#5
>>>>> %vreg3<def> = LWZ 28, %vreg65; mem:LD4[%sunkaddr355] GPRC:%vreg3 G8RC_and_G8RC_NOX0:%vreg65
>>>>> %vreg115<def> = CMPLWI %vreg3, 31; CRRC:%vreg115 GPRC:%vreg3
>>>>> BCC 47, %vreg115<kill>, <BB#9>; CRRC:%vreg115
>>>>> B <BB#8>
>>>>> Successors according to CFG: BB#9(0x7ffff800 / 0x80000000 = 100.00%) BB#8(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#8: derived from LLVM BB %cond.false.i.i
>>>>> Predecessors according to CFG: BB#7
>>>>> %vreg116<def> = ADDIStocHA %X2, <ga:@.str.97>; G8RC_and_G8RC_NOX0:%vreg116
>>>>> %vreg117<def> = LI8 1854; G8RC:%vreg117
>>>>> %vreg118<def> = ADDIStocHA %X2, <ga:@.str.23>; G8RC_and_G8RC_NOX0:%vreg118
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg119<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZNK4llvm8CallInst10getOperandEj>; G8RC_and_G8RC_NOX0:%vreg119
>>>>> %vreg120<def> = ADDItocL %vreg116<kill>, <ga:@.str.97>; G8RC:%vreg120 G8RC_and_G8RC_NOX0:%vreg116
>>>>> %vreg121<def> = ADDItocL %vreg118<kill>, <ga:@.str.23>; G8RC:%vreg121 G8RC_and_G8RC_NOX0:%vreg118
>>>>> %vreg122<def> = ADDItocL %vreg119<kill>, <ga:@__PRETTY_FUNCTION__._ZNK4llvm8CallInst10getOperandEj>; G8RC:%vreg122 G8RC_and_G8RC_NOX0:%vreg119
>>>>> %X3<def> = COPY %vreg120; G8RC:%vreg120
>>>>> %X4<def> = COPY %vreg121; G8RC:%vreg121
>>>>> %X5<def> = COPY %vreg117; G8RC:%vreg117
>>>>> %X6<def> = COPY %vreg122; G8RC:%vreg122
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#9: derived from LLVM BB %_ZNK4llvm8CallInst13getArgOperandEj.exit
>>>>> Predecessors according to CFG: BB#7
>>>>> %vreg124<def> = IMPLICIT_DEF; G8RC:%vreg124
>>>>> %vreg123<def,tied1> = INSERT_SUBREG %vreg124<tied0>, %vreg3, sub_32; G8RC:%vreg123,%vreg124 GPRC:%vreg3
>>>>> %vreg125<def> = RLWINM8 %vreg123<kill>, 28, 4, 31; G8RC:%vreg125,%vreg123
>>>>> %vreg126<def> = NEG8 %vreg125<kill>; G8RC:%vreg126,%vreg125
>>>>> %vreg127<def> = MULLI8 %vreg126<kill>, 24; G8RC:%vreg127,%vreg126
>>>>> %vreg128<def> = ADD8 %vreg65, %vreg127<kill>; G8RC_and_G8RC_NOX0:%vreg128,%vreg65 G8RC:%vreg127
>>>>> %vreg4<def> = LD 24, %vreg128<kill>; mem:LD8[%Val.i.i.i356](tbaa=!3) G8RC_and_G8RC_NOX0:%vreg4,%vreg128
>>>>> %vreg129<def> = CMPLDI %vreg4, 0; CRRC:%vreg129 G8RC_and_G8RC_NOX0:%vreg4
>>>>> BCC 71, %vreg129<kill>, <BB#11>; CRRC:%vreg129
>>>>> B <BB#10>
>>>>> Successors according to CFG: BB#10(0x00000800 / 0x80000000 = 0.00%) BB#11(0x7ffff800 / 0x80000000 = 100.00%)
>>>>>
>>>>> BB#10: derived from LLVM BB %cond.false.i.i.i.i.i
>>>>> Predecessors according to CFG: BB#9
>>>>> %vreg514<def> = ADDIStocHA %X2, <ga:@.str.26>; G8RC_and_G8RC_NOX0:%vreg514
>>>>> %vreg515<def> = LI8 95; G8RC:%vreg515
>>>>> %vreg516<def> = ADDIStocHA %X2, <ga:@.str.25>; G8RC_and_G8RC_NOX0:%vreg516
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg517<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZN4llvm11isa_impl_clINS_21ConstantAggregateZeroEPKNS_5ValueEE4doitES4_>; G8RC_and_G8RC_NOX0:%vreg517
>>>>> %vreg518<def> = ADDItocL %vreg514<kill>, <ga:@.str.26>; G8RC:%vreg518 G8RC_and_G8RC_NOX0:%vreg514
>>>>> %vreg519<def> = ADDItocL %vreg516<kill>, <ga:@.str.25>; G8RC:%vreg519 G8RC_and_G8RC_NOX0:%vreg516
>>>>> %vreg520<def> = ADDItocL %vreg517<kill>, <ga:@__PRETTY_FUNCTION__._ZN4llvm11isa_impl_clINS_21ConstantAggregateZeroEPKNS_5ValueEE4doitES4_>; G8RC:%vreg520 G8RC_and_G8RC_NOX0:%vreg517
>>>>> %X3<def> = COPY %vreg518; G8RC:%vreg518
>>>>> %X4<def> = COPY %vreg519; G8RC:%vreg519
>>>>> %X5<def> = COPY %vreg515; G8RC:%vreg515
>>>>> %X6<def> = COPY %vreg520; G8RC:%vreg520
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#11: derived from LLVM BB %_ZN4llvm8dyn_castINS_11ConstantIntENS_5ValueEEENS_10cast_rettyIT_PT0_E8ret_typeES6_.exit
>>>>> Predecessors according to CFG: BB#9
>>>>> %vreg131<def> = LBZ 24, %vreg4; mem:LD1[%SubclassID.i.i.i.i.i.i.i.i](align=8)(tbaa=!20) GPRC:%vreg131 G8RC_and_G8RC_NOX0:%vreg4
>>>>> %vreg132<def> = CMPLWI %vreg131, 13; CRRC:%vreg132 GPRC:%vreg131
>>>>> %vreg130<def> = LI8 0; G8RC_and_G8RC_NOX0:%vreg130
>>>>> %vreg133<def> = CMPWI %vreg131, 11; CRRC:%vreg133 GPRC:%vreg131
>>>>> BCC 76, %vreg132, <BB#135>; CRRC:%vreg132
>>>>> Successors according to CFG: BB#134(?%) BB#135(?%)
>>>>>
>>>>> BB#134: derived from LLVM BB %_ZN4llvm8dyn_castINS_11ConstantIntENS_5ValueEEENS_10cast_rettyIT_PT0_E8ret_typeES6_.exit
>>>>> Predecessors according to CFG: BB#11
>>>>> Successors according to CFG: BB#135(?%)
>>>>>
>>>>> BB#135: derived from LLVM BB %_ZN4llvm8dyn_castINS_11ConstantIntENS_5ValueEEENS_10cast_rettyIT_PT0_E8ret_typeES6_.exit
>>>>> Predecessors according to CFG: BB#11 BB#134
>>>>> %vreg5<def> = PHI %vreg130, <BB#134>, %vreg4, <BB#11>; G8RC_and_G8RC_NOX0:%vreg5,%vreg130,%vreg4
>>>>> %vreg134<def> = CMPDI %vreg5, 0; CRRC:%vreg134 G8RC_and_G8RC_NOX0:%vreg5
>>>>> %vreg135<def> = COPY %vreg133:sub_eq; CRBITRC:%vreg135 CRRC:%vreg133
>>>>> %vreg136<def> = COPY %vreg134:sub_eq; CRBITRC:%vreg136 CRRC:%vreg134
>>>>> %vreg137<def> = CRORC %vreg135<kill>, %vreg136; CRBITRC:%vreg137,%vreg135,%vreg136
>>>>> %vreg138<def> = CMPLWI %vreg131, 14; CRRC:%vreg138 GPRC:%vreg131
>>>>> BCC 76, %vreg138, <BB#137>; CRRC:%vreg138
>>>>> Successors according to CFG: BB#136(?%) BB#137(?%)
>>>>>
>>>>> BB#136: derived from LLVM BB %_ZN4llvm8dyn_castINS_11ConstantIntENS_5ValueEEENS_10cast_rettyIT_PT0_E8ret_typeES6_.exit
>>>>> Predecessors according to CFG: BB#135
>>>>> Successors according to CFG: BB#137(?%)
>>>>>
>>>>> BB#137: derived from LLVM BB %_ZN4llvm8dyn_castINS_11ConstantIntENS_5ValueEEENS_10cast_rettyIT_PT0_E8ret_typeES6_.exit
>>>>> Predecessors according to CFG: BB#135 BB#136
>>>>> %vreg6<def> = PHI %vreg130, <BB#136>, %vreg4, <BB#135>; G8RC_and_G8RC_NOX0:%vreg6,%vreg130,%vreg4
>>>>> %vreg139<def> = CMPDI %vreg6, 0; CRRC:%vreg139 G8RC_and_G8RC_NOX0:%vreg6
>>>>> %vreg140<def> = COPY %vreg139:sub_eq; CRBITRC:%vreg140 CRRC:%vreg139
>>>>> %vreg141<def> = CRORC %vreg137<kill>, %vreg140; CRBITRC:%vreg141,%vreg137,%vreg140
>>>>> BCn %vreg141<kill>, <BB#116>; CRBITRC:%vreg141
>>>>> B <BB#12>
>>>>> Successors according to CFG: BB#12(0x40000000 / 0x80000000 = 50.00%) BB#116(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#12: derived from LLVM BB %_ZN4llvm5APIntC2Ejmb.exit
>>>>> Predecessors according to CFG: BB#137
>>>>> %vreg7<def> = CRNOR %vreg136, %vreg136; CRBITRC:%vreg7,%vreg136,%vreg136
>>>>> %vreg142<def> = LI 64; GPRC:%vreg142
>>>>> %vreg143<def> = LI8 0; G8RC:%vreg143
>>>>> STW %vreg142<kill>, 0, <fi#0>; mem:ST4[%BitWidth.i357](align=8)(tbaa=!15) GPRC:%vreg142
>>>>> STD %vreg143<kill>, 8, <fi#0>; mem:ST8[%VAL.i](tbaa=!8) G8RC:%vreg143
>>>>> BCn %vreg7, <BB#34>; CRBITRC:%vreg7
>>>>> B <BB#13>
>>>>> Successors according to CFG: BB#13(0x50000000 / 0x80000000 = 62.50%) BB#34(0x30000000 / 0x80000000 = 37.50%)
>>>>>
>>>>> BB#13: derived from LLVM BB %if.then13
>>>>> Predecessors according to CFG: BB#12
>>>>> %vreg10<def> = LD 8, %vreg5; mem:LD8[%VTy.i.i](tbaa=!20) G8RC_and_G8RC_NOX0:%vreg10,%vreg5
>>>>> %vreg153<def> = CMPLDI %vreg10, 0; CRRC:%vreg153 G8RC_and_G8RC_NOX0:%vreg10
>>>>> BCC 71, %vreg153<kill>, <BB#15>; CRRC:%vreg153
>>>>> B <BB#14>
>>>>> Successors according to CFG: BB#14(0x00000800 / 0x80000000 = 0.00%) BB#15(0x7ffff800 / 0x80000000 = 100.00%)
>>>>>
>>>>> BB#14: derived from LLVM BB %cond.false.i.i.i.i.i.i
>>>>> Predecessors according to CFG: BB#13
>>>>> %vreg507<def> = ADDIStocHA %X2, <ga:@.str.26>; G8RC_and_G8RC_NOX0:%vreg507
>>>>> %vreg508<def> = LI8 95; G8RC:%vreg508
>>>>> %vreg509<def> = ADDIStocHA %X2, <ga:@.str.25>; G8RC_and_G8RC_NOX0:%vreg509
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg510<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZN4llvm11isa_impl_clINS_10VectorTypeEPKNS_4TypeEE4doitES4_>; G8RC_and_G8RC_NOX0:%vreg510
>>>>> %vreg511<def> = ADDItocL %vreg507<kill>, <ga:@.str.26>; G8RC:%vreg511 G8RC_and_G8RC_NOX0:%vreg507
>>>>> %vreg512<def> = ADDItocL %vreg509<kill>, <ga:@.str.25>; G8RC:%vreg512 G8RC_and_G8RC_NOX0:%vreg509
>>>>> %vreg513<def> = ADDItocL %vreg510<kill>, <ga:@__PRETTY_FUNCTION__._ZN4llvm11isa_impl_clINS_10VectorTypeEPKNS_4TypeEE4doitES4_>; G8RC:%vreg513 G8RC_and_G8RC_NOX0:%vreg510
>>>>> %X3<def> = COPY %vreg511; G8RC:%vreg511
>>>>> %X4<def> = COPY %vreg512; G8RC:%vreg512
>>>>> %X5<def> = COPY %vreg508; G8RC:%vreg508
>>>>> %X6<def> = COPY %vreg513; G8RC:%vreg513
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#15: derived from LLVM BB %_ZN4llvm3isaINS_10VectorTypeEPNS_4TypeEEEbRKT0_.exit.i.i
>>>>> Predecessors according to CFG: BB#13
>>>>> %vreg11<def> = LWZ 8, %vreg10; mem:LD4[%ID.i.i.i.i.i.i.i.i.i](align=8) GPRC:%vreg11 G8RC_and_G8RC_NOX0:%vreg10
>>>>> %vreg154<def> = RLWINM %vreg11, 8, 24, 31; GPRC:%vreg154,%vreg11
>>>>> %vreg155<def> = CMPLWI %vreg154, 16; CRRC:%vreg155 GPRC:%vreg154
>>>>> BCC 79, %vreg155<kill>, <BB#17>; CRRC:%vreg155
>>>>> B <BB#16>
>>>>> Successors according to CFG: BB#17(0x7ffff800 / 0x80000000 = 100.00%) BB#16(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#16: derived from LLVM BB %cond.false.i.i147
>>>>> Predecessors according to CFG: BB#15
>>>>> %vreg156<def> = ADDIStocHA %X2, <ga:@.str.24>; G8RC_and_G8RC_NOX0:%vreg156
>>>>> %vreg157<def> = LI8 237; G8RC:%vreg157
>>>>> %vreg158<def> = ADDIStocHA %X2, <ga:@.str.25>; G8RC_and_G8RC_NOX0:%vreg158
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg159<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZN4llvm4castINS_10VectorTypeENS_4TypeEEENS_10cast_rettyIT_PT0_E8ret_typeES6_>; G8RC_and_G8RC_NOX0:%vreg159
>>>>> %vreg160<def> = ADDItocL %vreg156<kill>, <ga:@.str.24>; G8RC:%vreg160 G8RC_and_G8RC_NOX0:%vreg156
>>>>> %vreg161<def> = ADDItocL %vreg158<kill>, <ga:@.str.25>; G8RC:%vreg161 G8RC_and_G8RC_NOX0:%vreg158
>>>>> %vreg162<def> = ADDItocL %vreg159<kill>, <ga:@__PRETTY_FUNCTION__._ZN4llvm4castINS_10VectorTypeENS_4TypeEEENS_10cast_rettyIT_PT0_E8ret_typeES6_>; G8RC:%vreg162 G8RC_and_G8RC_NOX0:%vreg159
>>>>> %X3<def> = COPY %vreg160; G8RC:%vreg160
>>>>> %X4<def> = COPY %vreg161; G8RC:%vreg161
>>>>> %X5<def> = COPY %vreg157; G8RC:%vreg157
>>>>> %X6<def> = COPY %vreg162; G8RC:%vreg162
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#17: derived from LLVM BB %_ZN4llvm4castINS_10VectorTypeES1_EENS_10cast_rettyIT_PT0_E8ret_typeES5_.exit
>>>>> Predecessors according to CFG: BB#15
>>>>> %vreg164<def> = ORI %vreg154, 1; GPRC:%vreg164,%vreg154
>>>>> %vreg165<def> = CMPWI %vreg154, 16; CRRC:%vreg165 GPRC:%vreg154
>>>>> %vreg166<def> = CMPWI %vreg164<kill>, 15; CRRC:%vreg166 GPRC:%vreg164
>>>>> %vreg167<def> = COPY %vreg165:sub_eq; CRBITRC:%vreg167 CRRC:%vreg165
>>>>> %vreg168<def> = COPY %vreg166:sub_eq; CRBITRC:%vreg168 CRRC:%vreg166
>>>>> %vreg169<def> = CROR %vreg167<kill>, %vreg168<kill>; CRBITRC:%vreg169,%vreg167,%vreg168
>>>>> BC %vreg169<kill>, <BB#19>; CRBITRC:%vreg169
>>>>> B <BB#18>
>>>>> Successors according to CFG: BB#19(0x7ffff800 / 0x80000000 = 100.00%) BB#18(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#18: derived from LLVM BB %cond.false.i.i150
>>>>> Predecessors according to CFG: BB#17
>>>>> %vreg170<def> = ADDIStocHA %X2, <ga:@.str.27>; G8RC_and_G8RC_NOX0:%vreg170
>>>>> %vreg171<def> = LI8 355; G8RC:%vreg171
>>>>> %vreg172<def> = ADDIStocHA %X2, <ga:@.str.28>; G8RC_and_G8RC_NOX0:%vreg172
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg173<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZNK4llvm4Type24getSequentialElementTypeEv>; G8RC_and_G8RC_NOX0:%vreg173
>>>>> %vreg174<def> = ADDItocL %vreg170<kill>, <ga:@.str.27>; G8RC:%vreg174 G8RC_and_G8RC_NOX0:%vreg170
>>>>> %vreg175<def> = ADDItocL %vreg172<kill>, <ga:@.str.28>; G8RC:%vreg175 G8RC_and_G8RC_NOX0:%vreg172
>>>>> %vreg176<def> = ADDItocL %vreg173<kill>, <ga:@__PRETTY_FUNCTION__._ZNK4llvm4Type24getSequentialElementTypeEv>; G8RC:%vreg176 G8RC_and_G8RC_NOX0:%vreg173
>>>>> %X3<def> = COPY %vreg174; G8RC:%vreg174
>>>>> %X4<def> = COPY %vreg175; G8RC:%vreg175
>>>>> %X5<def> = COPY %vreg171; G8RC:%vreg171
>>>>> %X6<def> = COPY %vreg176; G8RC:%vreg176
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#19: derived from LLVM BB %_ZNK4llvm14SequentialType14getElementTypeEv.exit
>>>>> Predecessors according to CFG: BB#17
>>>>> %vreg177<def> = LD 16, %vreg10; mem:LD8[%15](tbaa=!24) G8RC_and_G8RC_NOX0:%vreg177,%vreg10
>>>>> %vreg178<def> = LD 0, %vreg177<kill>; mem:LD8[%16](tbaa=!4) G8RC:%vreg178 G8RC_and_G8RC_NOX0:%vreg177
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg178; G8RC:%vreg178
>>>>> BL8_NOP <ga:@_ZNK4llvm4Type22getPrimitiveSizeInBitsEv>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X2<imp-use>, %R1<imp-def>, %X3<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg179<def> = COPY %X3; G8RC:%vreg179
>>>>> %vreg180<def> = LI 64; GPRC:%vreg180
>>>>> %vreg12<def> = COPY %vreg179:sub_32; GPRC:%vreg12 G8RC:%vreg179
>>>>> %vreg181<def> = DIVWU %vreg180, %vreg12; GPRC_and_GPRC_NOR0:%vreg181 GPRC:%vreg180,%vreg12
>>>>> %vreg182<def> = MULLW %vreg181, %vreg12; GPRC:%vreg182,%vreg12 GPRC_and_GPRC_NOR0:%vreg181
>>>>> %vreg183<def> = CMPLWI %vreg182<kill>, 64; CRRC:%vreg183 GPRC:%vreg182
>>>>> BCC 79, %vreg183<kill>, <BB#21>; CRRC:%vreg183
>>>>> B <BB#20>
>>>>> Successors according to CFG: BB#21(0x7ffff800 / 0x80000000 = 100.00%) BB#20(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#20: derived from LLVM BB %cond.false19
>>>>> Predecessors according to CFG: BB#19
>>>>> %vreg184<def> = ADDIStocHA %X2, <ga:@.str.84>; G8RC_and_G8RC_NOX0:%vreg184
>>>>> %vreg185<def> = LI8 263; G8RC:%vreg185
>>>>> %vreg186<def> = ADDIStocHA %X2, <ga:@.str.1>; G8RC_and_G8RC_NOX0:%vreg186
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg187<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZL19simplifyX86immShiftRKN4llvm13IntrinsicInstERNS_9IRBuilderILb1ENS_12TargetFolderENS_21InstCombineIRInserterEEE>; G8RC_and_G8RC_NOX0:%vreg187
>>>>> %vreg188<def> = ADDItocL %vreg184<kill>, <ga:@.str.84>; G8RC:%vreg188 G8RC_and_G8RC_NOX0:%vreg184
>>>>> %vreg189<def> = ADDItocL %vreg186<kill>, <ga:@.str.1>; G8RC:%vreg189 G8RC_and_G8RC_NOX0:%vreg186
>>>>> %vreg190<def> = ADDItocL %vreg187<kill>, <ga:@__PRETTY_FUNCTION__._ZL19simplifyX86immShiftRKN4llvm13IntrinsicInstERNS_9IRBuilderILb1ENS_12TargetFolderENS_21InstCombineIRInserterEEE>; G8RC:%vreg190 G8RC_and_G8RC_NOX0:%vreg187
>>>>> %X3<def> = COPY %vreg188; G8RC:%vreg188
>>>>> %X4<def> = COPY %vreg189; G8RC:%vreg189
>>>>> %X5<def> = COPY %vreg185; G8RC:%vreg185
>>>>> %X6<def> = COPY %vreg190; G8RC:%vreg190
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#21: derived from LLVM BB %cond.end20
>>>>> Predecessors according to CFG: BB#19
>>>>> %vreg192<def> = CMPLWI %vreg181, 0; CRRC:%vreg192 GPRC_and_GPRC_NOR0:%vreg181
>>>>> BCC 76, %vreg192<kill>, <BB#39>; CRRC:%vreg192
>>>>> B <BB#22>
>>>>> Successors according to CFG: BB#39(0x30000000 / 0x80000000 = 37.50%) BB#22(0x50000000 / 0x80000000 = 62.50%)
>>>>>
>>>>> BB#22: derived from LLVM BB %for.body.lr.ph
>>>>> Predecessors according to CFG: BB#21
>>>>> %vreg193<def> = LI 0; GPRC:%vreg193
>>>>> %vreg14<def> = ADDI %vreg181, -1; GPRC:%vreg14 GPRC_and_GPRC_NOR0:%vreg181
>>>>> %vreg196<def> = IMPLICIT_DEF; G8RC:%vreg196
>>>>> %vreg210<def> = IMPLICIT_DEF; G8RC:%vreg210
>>>>> %vreg209<def,tied1> = INSERT_SUBREG %vreg210<tied0>, %vreg12, sub_32; G8RC:%vreg209,%vreg210 GPRC:%vreg12
>>>>> %vreg211<def> = RLDICL %vreg209, 0, 32; G8RC:%vreg211,%vreg209
>>>>> %vreg212<def> = ADDI8 <fi#1>, 0; G8RC:%vreg212
>>>>> %vreg213<def> = ADDI8 <fi#0>, 0; G8RC:%vreg213
>>>>> %vreg221<def> = ADDI8 <fi#2>, 0; G8RC:%vreg221
>>>>> %vreg222<def> = LI8 64; G8RC:%vreg222
>>>>> Successors according to CFG: BB#23(?%)
>>>>>
>>>>> BB#23: derived from LLVM BB %for.body
>>>>> Predecessors according to CFG: BB#22 BB#33
>>>>> %vreg15<def> = PHI %vreg193, <BB#22>, %vreg19, <BB#33>; GPRC_and_GPRC_NOR0:%vreg15 GPRC:%vreg193,%vreg19
>>>>> %vreg194<def> = SUBF %vreg15, %vreg14; GPRC:%vreg194,%vreg14 GPRC_and_GPRC_NOR0:%vreg15
>>>>> %vreg195<def,tied1> = INSERT_SUBREG %vreg196<tied0>, %vreg194<kill>, sub_32; G8RC:%vreg195,%vreg196 GPRC:%vreg194
>>>>> %vreg197<def> = RLDICL %vreg195<kill>, 0, 32; G8RC:%vreg197,%vreg195
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg5; G8RC_and_G8RC_NOX0:%vreg5
>>>>> %X4<def> = COPY %vreg197; G8RC:%vreg197
>>>>> BL8_NOP <ga:@_ZNK4llvm22ConstantDataSequential20getElementAsConstantEj>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X2<imp-use>, %R1<imp-def>, %X3<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg198<def> = COPY %X3; G8RC_and_G8RC_NOX0:%vreg198
>>>>> %vreg199<def> = CMPLDI %vreg198, 0; CRRC:%vreg199 G8RC_and_G8RC_NOX0:%vreg198
>>>>> BCC 71, %vreg199<kill>, <BB#25>; CRRC:%vreg199
>>>>> B <BB#24>
>>>>> Successors according to CFG: BB#24(0x00000800 / 0x80000000 = 0.00%) BB#25(0x7ffff800 / 0x80000000 = 100.00%)
>>>>>
>>>>> BB#24: derived from LLVM BB %cond.false.i.i.i.i.i152
>>>>> Predecessors according to CFG: BB#23
>>>>> %vreg229<def> = ADDIStocHA %X2, <ga:@.str.26>; G8RC_and_G8RC_NOX0:%vreg229
>>>>> %vreg230<def> = LI8 95; G8RC:%vreg230
>>>>> %vreg231<def> = ADDIStocHA %X2, <ga:@.str.25>; G8RC_and_G8RC_NOX0:%vreg231
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg232<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZN4llvm11isa_impl_clINS_11ConstantIntEPKNS_8ConstantEE4doitES4_>; G8RC_and_G8RC_NOX0:%vreg232
>>>>> %vreg233<def> = ADDItocL %vreg229<kill>, <ga:@.str.26>; G8RC:%vreg233 G8RC_and_G8RC_NOX0:%vreg229
>>>>> %vreg234<def> = ADDItocL %vreg231<kill>, <ga:@.str.25>; G8RC:%vreg234 G8RC_and_G8RC_NOX0:%vreg231
>>>>> %vreg235<def> = ADDItocL %vreg232<kill>, <ga:@__PRETTY_FUNCTION__._ZN4llvm11isa_impl_clINS_11ConstantIntEPKNS_8ConstantEE4doitES4_>; G8RC:%vreg235 G8RC_and_G8RC_NOX0:%vreg232
>>>>> %X3<def> = COPY %vreg233; G8RC:%vreg233
>>>>> %X4<def> = COPY %vreg234; G8RC:%vreg234
>>>>> %X5<def> = COPY %vreg230; G8RC:%vreg230
>>>>> %X6<def> = COPY %vreg235; G8RC:%vreg235
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#25: derived from LLVM BB %_ZN4llvm3isaINS_11ConstantIntEPNS_8ConstantEEEbRKT0_.exit.i
>>>>> Predecessors according to CFG: BB#23
>>>>> %vreg16<def> = COPY %vreg198; G8RC_and_G8RC_NOX0:%vreg16,%vreg198
>>>>> %vreg200<def> = LBZ 24, %vreg16; mem:LD1[%SubclassID.i.i.i.i.i.i.i.i153](align=8)(tbaa=!20) GPRC:%vreg200 G8RC_and_G8RC_NOX0:%vreg16
>>>>> %vreg201<def> = CMPLWI %vreg200<kill>, 14; CRRC:%vreg201 GPRC:%vreg200
>>>>> BCC 79, %vreg201<kill>, <BB#27>; CRRC:%vreg201
>>>>> B <BB#26>
>>>>> Successors according to CFG: BB#27(0x7ffff800 / 0x80000000 = 100.00%) BB#26(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#26: derived from LLVM BB %cond.false.i155
>>>>> Predecessors according to CFG: BB#25
>>>>> %vreg202<def> = ADDIStocHA %X2, <ga:@.str.24>; G8RC_and_G8RC_NOX0:%vreg202
>>>>> %vreg203<def> = LI8 237; G8RC:%vreg203
>>>>> %vreg204<def> = ADDIStocHA %X2, <ga:@.str.25>; G8RC_and_G8RC_NOX0:%vreg204
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg205<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZN4llvm4castINS_11ConstantIntENS_8ConstantEEENS_10cast_rettyIT_PT0_E8ret_typeES6_>; G8RC_and_G8RC_NOX0:%vreg205
>>>>> %vreg206<def> = ADDItocL %vreg202<kill>, <ga:@.str.24>; G8RC:%vreg206 G8RC_and_G8RC_NOX0:%vreg202
>>>>> %vreg207<def> = ADDItocL %vreg204<kill>, <ga:@.str.25>; G8RC:%vreg207 G8RC_and_G8RC_NOX0:%vreg204
>>>>> %vreg208<def> = ADDItocL %vreg205<kill>, <ga:@__PRETTY_FUNCTION__._ZN4llvm4castINS_11ConstantIntENS_8ConstantEEENS_10cast_rettyIT_PT0_E8ret_typeES6_>; G8RC:%vreg208 G8RC_and_G8RC_NOX0:%vreg205
>>>>> %X3<def> = COPY %vreg206; G8RC:%vreg206
>>>>> %X4<def> = COPY %vreg207; G8RC:%vreg207
>>>>> %X5<def> = COPY %vreg203; G8RC:%vreg203
>>>>> %X6<def> = COPY %vreg208; G8RC:%vreg208
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#27: derived from LLVM BB %_ZN4llvm4castINS_11ConstantIntENS_8ConstantEEENS_10cast_rettyIT_PT0_E8ret_typeES6_.exit
>>>>> Predecessors according to CFG: BB#25
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg212; G8RC:%vreg212
>>>>> %X4<def> = COPY %vreg213; G8RC:%vreg213
>>>>> %X5<def> = COPY %vreg211; G8RC:%vreg211
>>>>> BL8_NOP <ga:@_ZNK4llvm5APInt3shlEj>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg214<def> = LWZ 0, <fi#0>; mem:LD4[%20](align=8)(tbaa=!15) GPRC:%vreg214
>>>>> %vreg215<def> = CMPLWI %vreg214<kill>, 65; CRRC:%vreg215 GPRC:%vreg214
>>>>> BCC 12, %vreg215<kill>, <BB#30>; CRRC:%vreg215
>>>>> B <BB#28>
>>>>> Successors according to CFG: BB#30(0x40000000 / 0x80000000 = 50.00%) BB#28(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#28: derived from LLVM BB %if.then.i
>>>>> Predecessors according to CFG: BB#27
>>>>> %vreg17<def> = LD 8, <fi#0>; mem:LD8[%sunkaddr362](tbaa=!4) G8RC:%vreg17
>>>>> %vreg216<def> = CMPLDI %vreg17, 0; CRRC:%vreg216 G8RC:%vreg17
>>>>> BCC 76, %vreg216<kill>, <BB#30>; CRRC:%vreg216
>>>>> B <BB#29>
>>>>> Successors according to CFG: BB#30(0x30000000 / 0x80000000 = 37.50%) BB#29(0x50000000 / 0x80000000 = 62.50%)
>>>>>
>>>>> BB#29: derived from LLVM BB %delete.notnull.i
>>>>> Predecessors according to CFG: BB#28
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg17; G8RC:%vreg17
>>>>> BL8_NOP <ga:@_ZdaPv>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> Successors according to CFG: BB#30(?%)
>>>>>
>>>>> BB#30: derived from LLVM BB %_ZN4llvm5APIntaSEOS0_.exit
>>>>> Predecessors according to CFG: BB#27 BB#28 BB#29
>>>>> %vreg217<def> = LD 8, <fi#1>; mem:LD8[%sunkaddr365] G8RC:%vreg217
>>>>> STD %vreg217<kill>, 8, <fi#0>; mem:ST8[%sunkaddr368] G8RC:%vreg217
>>>>> %vreg219<def> = LWZ 0, <fi#1>; mem:LD4[%25](align=8)(tbaa=!15) GPRC:%vreg219
>>>>> STW %vreg193, 0, <fi#1>; mem:ST4[%25](align=8)(tbaa=!15) GPRC:%vreg193
>>>>> %vreg220<def> = ADDI8 %vreg198, 32; G8RC:%vreg220 G8RC_and_G8RC_NOX0:%vreg198
>>>>> STW %vreg219<kill>, 0, <fi#0>; mem:ST4[%26](align=8)(tbaa=!15) GPRC:%vreg219
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg221; G8RC:%vreg221
>>>>> %X4<def> = COPY %vreg220; G8RC:%vreg220
>>>>> %X5<def> = COPY %vreg222; G8RC:%vreg222
>>>>> BL8_NOP <ga:@_ZNK4llvm5APInt11zextOrTruncEj>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg213; G8RC:%vreg213
>>>>> %X4<def> = COPY %vreg221; G8RC:%vreg221
>>>>> BL8_NOP <ga:@_ZN4llvm5APIntoRERKS0_>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X2<imp-use>, %R1<imp-def>, %X3<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg225<def> = LWZ 0, <fi#2>; mem:LD4[%24](align=8)(tbaa=!15) GPRC:%vreg225
>>>>> %vreg226<def> = CMPLWI %vreg225<kill>, 65; CRRC:%vreg226 GPRC:%vreg225
>>>>> BCC 12, %vreg226<kill>, <BB#33>; CRRC:%vreg226
>>>>> B <BB#31>
>>>>> Successors according to CFG: BB#31(0x40000000 / 0x80000000 = 50.00%) BB#33(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#31: derived from LLVM BB %if.then.i168
>>>>> Predecessors according to CFG: BB#30
>>>>> %vreg18<def> = LD 8, <fi#2>; mem:LD8[%sunkaddr371](tbaa=!4) G8RC:%vreg18
>>>>> %vreg227<def> = CMPLDI %vreg18, 0; CRRC:%vreg227 G8RC:%vreg18
>>>>> BCC 76, %vreg227<kill>, <BB#33>; CRRC:%vreg227
>>>>> B <BB#32>
>>>>> Successors according to CFG: BB#33(0x30000000 / 0x80000000 = 37.50%) BB#32(0x50000000 / 0x80000000 = 62.50%)
>>>>>
>>>>> BB#32: derived from LLVM BB %delete.notnull.i169
>>>>> Predecessors according to CFG: BB#31
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg18; G8RC:%vreg18
>>>>> BL8_NOP <ga:@_ZdaPv>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> Successors according to CFG: BB#33(?%)
>>>>>
>>>>> BB#33: derived from LLVM BB %_ZN4llvm5APIntD2Ev.exit170
>>>>> Predecessors according to CFG: BB#30 BB#31 BB#32
>>>>> %vreg19<def> = ADDI %vreg15, 1; GPRC:%vreg19 GPRC_and_GPRC_NOR0:%vreg15
>>>>> %vreg228<def> = CMPLW %vreg19, %vreg181; CRRC:%vreg228 GPRC:%vreg19 GPRC_and_GPRC_NOR0:%vreg181
>>>>> BCC 76, %vreg228<kill>, <BB#39>; CRRC:%vreg228
>>>>> B <BB#23>
>>>>> Successors according to CFG: BB#39(0x04000000 / 0x80000000 = 3.12%) BB#23(0x7c000000 / 0x80000000 = 96.88%)
>>>>>
>>>>> BB#34: derived from LLVM BB %if.else
>>>>> Predecessors according to CFG: BB#12
>>>>> %vreg8<def> = CRNOR %vreg140, %vreg140; CRBITRC:%vreg8,%vreg140,%vreg140
>>>>> BCn %vreg8, <BB#39>; CRBITRC:%vreg8
>>>>> B <BB#35>
>>>>> Successors according to CFG: BB#35(0x50000000 / 0x80000000 = 62.50%) BB#39(0x30000000 / 0x80000000 = 37.50%)
>>>>>
>>>>> BB#35: derived from LLVM BB %land.lhs.true.i
>>>>> Predecessors according to CFG: BB#34
>>>>> %vreg21<def>, %vreg144<def,tied3> = LWZU 32, %vreg6<tied1>; mem:LD4[%BitWidth.i12.i372](align=8) GPRC:%vreg21 G8RC_and_G8RC_NOX0:%vreg144,%vreg6
>>>>> %vreg145<def> = CMPLWI %vreg21, 64; CRRC:%vreg145 GPRC:%vreg21
>>>>> BCC 44, %vreg145<kill>, <BB#38>; CRRC:%vreg145
>>>>> B <BB#36>
>>>>> Successors according to CFG: BB#36(0x40000000 / 0x80000000 = 50.00%) BB#38(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#36: derived from LLVM BB %if.then.i175
>>>>> Predecessors according to CFG: BB#35
>>>>> %vreg22<def> = LD 40, %vreg6; mem:LD8[%VAL.i174](tbaa=!8) G8RC:%vreg22 G8RC_and_G8RC_NOX0:%vreg6
>>>>> %vreg23<def> = RLWINM %vreg21, 0, 26, 31; GPRC:%vreg23,%vreg21
>>>>> %vreg148<def> = CMPLWI %vreg23, 0; CRRC:%vreg148 GPRC:%vreg23
>>>>> STD %vreg22, 8, <fi#0>; mem:ST8[%sunkaddr375](tbaa=!8) G8RC:%vreg22
>>>>> STW %vreg21, 0, <fi#0>; mem:ST4[%34](align=8)(tbaa=!15) GPRC:%vreg21
>>>>> BCC 76, %vreg148<kill>, <BB#39>; CRRC:%vreg148
>>>>> B <BB#37>
>>>>> Successors according to CFG: BB#39(0x30000000 / 0x80000000 = 37.50%) BB#37(0x50000000 / 0x80000000 = 62.50%)
>>>>>
>>>>> BB#37: derived from LLVM BB %if.then2.i.i
>>>>> Predecessors according to CFG: BB#36
>>>>> %vreg149<def> = SUBFIC %vreg23, 64, %CARRY<imp-def,dead>; GPRC:%vreg149,%vreg23
>>>>> %vreg150<def> = LI8 65535; G8RC:%vreg150
>>>>> %vreg151<def> = SRD %vreg150<kill>, %vreg149<kill>; G8RC:%vreg151,%vreg150 GPRC:%vreg149
>>>>> %vreg152<def> = AND8 %vreg22, %vreg151<kill>; G8RC:%vreg152,%vreg22,%vreg151
>>>>> STD %vreg152<kill>, 8, <fi#0>; mem:ST8[%sunkaddr378](tbaa=!8) G8RC:%vreg152
>>>>> B <BB#39>
>>>>> Successors according to CFG: BB#39(?%)
>>>>>
>>>>> BB#38: derived from LLVM BB %if.end.i
>>>>> Predecessors according to CFG: BB#35
>>>>> %vreg20<def> = COPY %vreg144; G8RC:%vreg20 G8RC_and_G8RC_NOX0:%vreg144
>>>>> %vreg146<def> = ADDI8 <fi#0>, 0; G8RC:%vreg146
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg146; G8RC:%vreg146
>>>>> %X4<def> = COPY %vreg20; G8RC:%vreg20
>>>>> BL8_NOP <ga:@_ZN4llvm5APInt14AssignSlowCaseERKS0_>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X2<imp-use>, %R1<imp-def>, %X3<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> Successors according to CFG: BB#39(?%)
>>>>>
>>>>> BB#39: derived from LLVM BB %if.end34
>>>>> Predecessors according to CFG: BB#34 BB#38 BB#36 BB#37 BB#21 BB#33
>>>>> %vreg236<def> = LWZ 28, %vreg65; mem:LD4[%sunkaddr381] GPRC:%vreg236 G8RC_and_G8RC_NOX0:%vreg65
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg65; G8RC_and_G8RC_NOX0:%vreg65
>>>>> BL8_NOP <ga:@_ZNK4llvm17OperandBundleUserINS_8CallInstEPNS_3UseEE25getNumTotalBundleOperandsEv>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X2<imp-use>, %R1<imp-def>, %X3<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg237<def> = COPY %X3; G8RC:%vreg237
>>>>> %vreg238<def> = COPY %vreg237:sub_32; GPRC_and_GPRC_NOR0:%vreg238 G8RC:%vreg237
>>>>> %vreg239<def> = ADDI %vreg238<kill>, 1; GPRC:%vreg239 GPRC_and_GPRC_NOR0:%vreg238
>>>>> %vreg240<def> = RLWINM %vreg236, 28, 4, 31; GPRC:%vreg240,%vreg236
>>>>> %vreg241<def> = CMPLW %vreg240<kill>, %vreg239<kill>; CRRC:%vreg241 GPRC:%vreg240,%vreg239
>>>>> BCC 71, %vreg241<kill>, <BB#41>; CRRC:%vreg241
>>>>> B <BB#40>
>>>>> Successors according to CFG: BB#40(0x00000800 / 0x80000000 = 0.00%) BB#41(0x7ffff800 / 0x80000000 = 100.00%)
>>>>>
>>>>> BB#40: derived from LLVM BB %cond.false.i184
>>>>> Predecessors according to CFG: BB#39
>>>>> %vreg500<def> = ADDIStocHA %X2, <ga:@.str.22>; G8RC_and_G8RC_NOX0:%vreg500
>>>>> %vreg501<def> = LI8 1543; G8RC:%vreg501
>>>>> %vreg502<def> = ADDIStocHA %X2, <ga:@.str.23>; G8RC_and_G8RC_NOX0:%vreg502
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg503<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZNK4llvm8CallInst13getArgOperandEj>; G8RC_and_G8RC_NOX0:%vreg503
>>>>> %vreg504<def> = ADDItocL %vreg500<kill>, <ga:@.str.22>; G8RC:%vreg504 G8RC_and_G8RC_NOX0:%vreg500
>>>>> %vreg505<def> = ADDItocL %vreg502<kill>, <ga:@.str.23>; G8RC:%vreg505 G8RC_and_G8RC_NOX0:%vreg502
>>>>> %vreg506<def> = ADDItocL %vreg503<kill>, <ga:@__PRETTY_FUNCTION__._ZNK4llvm8CallInst13getArgOperandEj>; G8RC:%vreg506 G8RC_and_G8RC_NOX0:%vreg503
>>>>> %X3<def> = COPY %vreg504; G8RC:%vreg504
>>>>> %X4<def> = COPY %vreg505; G8RC:%vreg505
>>>>> %X5<def> = COPY %vreg501; G8RC:%vreg501
>>>>> %X6<def> = COPY %vreg506; G8RC:%vreg506
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#41: derived from LLVM BB %cond.end.i188
>>>>> Predecessors according to CFG: BB#39
>>>>> %vreg242<def> = LWZ 28, %vreg65; mem:LD4[%sunkaddr384] GPRC:%vreg242 G8RC_and_G8RC_NOX0:%vreg65
>>>>> %vreg24<def> = RLWINM %vreg242, 28, 4, 31; GPRC:%vreg24,%vreg242
>>>>> %vreg243<def> = CMPLWI %vreg24, 0; CRRC:%vreg243 GPRC:%vreg24
>>>>> BCC 71, %vreg243<kill>, <BB#43>; CRRC:%vreg243
>>>>> B <BB#42>
>>>>> Successors according to CFG: BB#42(0x00000800 / 0x80000000 = 0.00%) BB#43(0x7ffff800 / 0x80000000 = 100.00%)
>>>>>
>>>>> BB#42: derived from LLVM BB %cond.false.i.i189
>>>>> Predecessors according to CFG: BB#41
>>>>> %vreg493<def> = ADDIStocHA %X2, <ga:@.str.97>; G8RC_and_G8RC_NOX0:%vreg493
>>>>> %vreg494<def> = LI8 1854; G8RC:%vreg494
>>>>> %vreg495<def> = ADDIStocHA %X2, <ga:@.str.23>; G8RC_and_G8RC_NOX0:%vreg495
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg496<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZNK4llvm8CallInst10getOperandEj>; G8RC_and_G8RC_NOX0:%vreg496
>>>>> %vreg497<def> = ADDItocL %vreg493<kill>, <ga:@.str.97>; G8RC:%vreg497 G8RC_and_G8RC_NOX0:%vreg493
>>>>> %vreg498<def> = ADDItocL %vreg495<kill>, <ga:@.str.23>; G8RC:%vreg498 G8RC_and_G8RC_NOX0:%vreg495
>>>>> %vreg499<def> = ADDItocL %vreg496<kill>, <ga:@__PRETTY_FUNCTION__._ZNK4llvm8CallInst10getOperandEj>; G8RC:%vreg499 G8RC_and_G8RC_NOX0:%vreg496
>>>>> %X3<def> = COPY %vreg497; G8RC:%vreg497
>>>>> %X4<def> = COPY %vreg498; G8RC:%vreg498
>>>>> %X5<def> = COPY %vreg494; G8RC:%vreg494
>>>>> %X6<def> = COPY %vreg499; G8RC:%vreg499
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#43: derived from LLVM BB %_ZNK4llvm8CallInst13getArgOperandEj.exit194
>>>>> Predecessors according to CFG: BB#41
>>>>> %vreg245<def> = IMPLICIT_DEF; G8RC:%vreg245
>>>>> %vreg244<def,tied1> = INSERT_SUBREG %vreg245<tied0>, %vreg24, sub_32; G8RC:%vreg244,%vreg245 GPRC:%vreg24
>>>>> %vreg246<def> = RLDICL %vreg244<kill>, 0, 32; G8RC:%vreg246,%vreg244
>>>>> %vreg247<def> = NEG8 %vreg246<kill>; G8RC:%vreg247,%vreg246
>>>>> %vreg248<def> = MULLI8 %vreg247<kill>, 24; G8RC:%vreg248,%vreg247
>>>>> %vreg25<def> = LDX %vreg65, %vreg248<kill>; mem:LD8[%Val.i.i.i193](tbaa=!3) G8RC_and_G8RC_NOX0:%vreg25,%vreg65 G8RC:%vreg248
>>>>> %vreg26<def> = LD 8, %vreg25; mem:LD8[%VTy.i](tbaa=!20) G8RC_and_G8RC_NOX0:%vreg26,%vreg25
>>>>> %vreg249<def> = CMPLDI %vreg26, 0; CRRC:%vreg249 G8RC_and_G8RC_NOX0:%vreg26
>>>>> BCC 71, %vreg249<kill>, <BB#45>; CRRC:%vreg249
>>>>> B <BB#44>
>>>>> Successors according to CFG: BB#44(0x00000800 / 0x80000000 = 0.00%) BB#45(0x7ffff800 / 0x80000000 = 100.00%)
>>>>>
>>>>> BB#44: derived from LLVM BB %cond.false.i.i.i.i.i196
>>>>> Predecessors according to CFG: BB#43
>>>>> %vreg486<def> = ADDIStocHA %X2, <ga:@.str.26>; G8RC_and_G8RC_NOX0:%vreg486
>>>>> %vreg487<def> = LI8 95; G8RC:%vreg487
>>>>> %vreg488<def> = ADDIStocHA %X2, <ga:@.str.25>; G8RC_and_G8RC_NOX0:%vreg488
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg489<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZN4llvm11isa_impl_clINS_10VectorTypeEPKNS_4TypeEE4doitES4_>; G8RC_and_G8RC_NOX0:%vreg489
>>>>> %vreg490<def> = ADDItocL %vreg486<kill>, <ga:@.str.26>; G8RC:%vreg490 G8RC_and_G8RC_NOX0:%vreg486
>>>>> %vreg491<def> = ADDItocL %vreg488<kill>, <ga:@.str.25>; G8RC:%vreg491 G8RC_and_G8RC_NOX0:%vreg488
>>>>> %vreg492<def> = ADDItocL %vreg489<kill>, <ga:@__PRETTY_FUNCTION__._ZN4llvm11isa_impl_clINS_10VectorTypeEPKNS_4TypeEE4doitES4_>; G8RC:%vreg492 G8RC_and_G8RC_NOX0:%vreg489
>>>>> %X3<def> = COPY %vreg490; G8RC:%vreg490
>>>>> %X4<def> = COPY %vreg491; G8RC:%vreg491
>>>>> %X5<def> = COPY %vreg487; G8RC:%vreg487
>>>>> %X6<def> = COPY %vreg492; G8RC:%vreg492
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#45: derived from LLVM BB %_ZN4llvm3isaINS_10VectorTypeEPNS_4TypeEEEbRKT0_.exit.i
>>>>> Predecessors according to CFG: BB#43
>>>>> %vreg27<def> = LWZ 8, %vreg26; mem:LD4[%ID.i.i.i.i.i.i.i.i](align=8) GPRC:%vreg27 G8RC_and_G8RC_NOX0:%vreg26
>>>>> %vreg250<def> = RLWINM %vreg27, 8, 24, 31; GPRC:%vreg250,%vreg27
>>>>> %vreg251<def> = CMPLWI %vreg250, 16; CRRC:%vreg251 GPRC:%vreg250
>>>>> BCC 79, %vreg251<kill>, <BB#47>; CRRC:%vreg251
>>>>> B <BB#46>
>>>>> Successors according to CFG: BB#47(0x7ffff800 / 0x80000000 = 100.00%) BB#46(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#46: derived from LLVM BB %cond.false.i198
>>>>> Predecessors according to CFG: BB#45
>>>>> %vreg252<def> = ADDIStocHA %X2, <ga:@.str.24>; G8RC_and_G8RC_NOX0:%vreg252
>>>>> %vreg253<def> = LI8 237; G8RC:%vreg253
>>>>> %vreg254<def> = ADDIStocHA %X2, <ga:@.str.25>; G8RC_and_G8RC_NOX0:%vreg254
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg255<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZN4llvm4castINS_10VectorTypeENS_4TypeEEENS_10cast_rettyIT_PT0_E8ret_typeES6_>; G8RC_and_G8RC_NOX0:%vreg255
>>>>> %vreg256<def> = ADDItocL %vreg252<kill>, <ga:@.str.24>; G8RC:%vreg256 G8RC_and_G8RC_NOX0:%vreg252
>>>>> %vreg257<def> = ADDItocL %vreg254<kill>, <ga:@.str.25>; G8RC:%vreg257 G8RC_and_G8RC_NOX0:%vreg254
>>>>> %vreg258<def> = ADDItocL %vreg255<kill>, <ga:@__PRETTY_FUNCTION__._ZN4llvm4castINS_10VectorTypeENS_4TypeEEENS_10cast_rettyIT_PT0_E8ret_typeES6_>; G8RC:%vreg258 G8RC_and_G8RC_NOX0:%vreg255
>>>>> %X3<def> = COPY %vreg256; G8RC:%vreg256
>>>>> %X4<def> = COPY %vreg257; G8RC:%vreg257
>>>>> %X5<def> = COPY %vreg253; G8RC:%vreg253
>>>>> %X6<def> = COPY %vreg258; G8RC:%vreg258
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#47: derived from LLVM BB %_ZN4llvm4castINS_10VectorTypeENS_4TypeEEENS_10cast_rettyIT_PT0_E8ret_typeES6_.exit
>>>>> Predecessors according to CFG: BB#45
>>>>> %vreg260<def> = ORI %vreg250, 1; GPRC:%vreg260,%vreg250
>>>>> %vreg261<def> = CMPWI %vreg250, 16; CRRC:%vreg261 GPRC:%vreg250
>>>>> %vreg262<def> = CMPWI %vreg260<kill>, 15; CRRC:%vreg262 GPRC:%vreg260
>>>>> %vreg263<def> = COPY %vreg261:sub_eq; CRBITRC:%vreg263 CRRC:%vreg261
>>>>> %vreg264<def> = COPY %vreg262:sub_eq; CRBITRC:%vreg264 CRRC:%vreg262
>>>>> %vreg265<def> = CROR %vreg263<kill>, %vreg264<kill>; CRBITRC:%vreg265,%vreg263,%vreg264
>>>>> BC %vreg265<kill>, <BB#49>; CRBITRC:%vreg265
>>>>> B <BB#48>
>>>>> Successors according to CFG: BB#49(0x7ffff800 / 0x80000000 = 100.00%) BB#48(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#48: derived from LLVM BB %cond.false.i.i205
>>>>> Predecessors according to CFG: BB#47
>>>>> %vreg266<def> = ADDIStocHA %X2, <ga:@.str.27>; G8RC_and_G8RC_NOX0:%vreg266
>>>>> %vreg267<def> = LI8 355; G8RC:%vreg267
>>>>> %vreg268<def> = ADDIStocHA %X2, <ga:@.str.28>; G8RC_and_G8RC_NOX0:%vreg268
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg269<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZNK4llvm4Type24getSequentialElementTypeEv>; G8RC_and_G8RC_NOX0:%vreg269
>>>>> %vreg270<def> = ADDItocL %vreg266<kill>, <ga:@.str.27>; G8RC:%vreg270 G8RC_and_G8RC_NOX0:%vreg266
>>>>> %vreg271<def> = ADDItocL %vreg268<kill>, <ga:@.str.28>; G8RC:%vreg271 G8RC_and_G8RC_NOX0:%vreg268
>>>>> %vreg272<def> = ADDItocL %vreg269<kill>, <ga:@__PRETTY_FUNCTION__._ZNK4llvm4Type24getSequentialElementTypeEv>; G8RC:%vreg272 G8RC_and_G8RC_NOX0:%vreg269
>>>>> %X3<def> = COPY %vreg270; G8RC:%vreg270
>>>>> %X4<def> = COPY %vreg271; G8RC:%vreg271
>>>>> %X5<def> = COPY %vreg267; G8RC:%vreg267
>>>>> %X6<def> = COPY %vreg272; G8RC:%vreg272
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#49: derived from LLVM BB %_ZNK4llvm14SequentialType14getElementTypeEv.exit207
>>>>> Predecessors according to CFG: BB#47
>>>>> %vreg273<def> = LD 16, %vreg26; mem:LD8[%43](tbaa=!24) G8RC_and_G8RC_NOX0:%vreg273,%vreg26
>>>>> %vreg29<def> = LWZ 32, %vreg26; mem:LD4[%46](align=8)(tbaa=!108) GPRC:%vreg29 G8RC_and_G8RC_NOX0:%vreg26
>>>>> %vreg28<def> = LD 0, %vreg273<kill>; mem:LD8[%44](tbaa=!4) G8RC:%vreg28 G8RC_and_G8RC_NOX0:%vreg273
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg28; G8RC:%vreg28
>>>>> BL8_NOP <ga:@_ZNK4llvm4Type22getPrimitiveSizeInBitsEv>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X2<imp-use>, %R1<imp-def>, %X3<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg274<def> = COPY %X3; G8RC:%vreg274
>>>>> %vreg31<def> = LWZ 0, <fi#0>; mem:LD4[%42](align=8)(tbaa=!15) GPRC:%vreg31
>>>>> %vreg30<def> = COPY %vreg274:sub_32; GPRC_and_GPRC_NOR0:%vreg30 G8RC:%vreg274
>>>>> %vreg275<def> = CMPLWI %vreg31, 64; CRRC:%vreg275 GPRC:%vreg31
>>>>> BCC 44, %vreg275<kill>, <BB#52>; CRRC:%vreg275
>>>>> B <BB#50>
>>>>> Successors according to CFG: BB#50(0x40000000 / 0x80000000 = 50.00%) BB#52(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#50: derived from LLVM BB %if.then.i212
>>>>> Predecessors according to CFG: BB#49
>>>>> %vreg285<def> = LD 8, <fi#0>; mem:LD8[%sunkaddr387](tbaa=!8) G8RC:%vreg285
>>>>> %vreg286<def> = CMPLDI %vreg285<kill>, 0; CRRC:%vreg286 G8RC:%vreg285
>>>>> BCC 76, %vreg286<kill>, <BB#112>; CRRC:%vreg286
>>>>> B <BB#51>
>>>>> Successors according to CFG: BB#112(0x30000000 / 0x80000000 = 37.50%) BB#51(0x50000000 / 0x80000000 = 62.50%)
>>>>>
>>>>> BB#51: derived from LLVM BB %if.end45.thread
>>>>> Predecessors according to CFG: BB#50
>>>>> %vreg288<def> = IMPLICIT_DEF; G8RC:%vreg288
>>>>> %vreg287<def,tied1> = INSERT_SUBREG %vreg288<tied0>, %vreg30, sub_32; G8RC:%vreg287,%vreg288 GPRC_and_GPRC_NOR0:%vreg30
>>>>> %vreg32<def> = RLDICL %vreg287<kill>, 0, 32; G8RC:%vreg32,%vreg287
>>>>> B <BB#54>
>>>>> Successors according to CFG: BB#54(?%)
>>>>>
>>>>> BB#52: derived from LLVM BB %_ZNK4llvm5APInteqEm.exit
>>>>> Predecessors according to CFG: BB#49
>>>>> %vreg276<def> = ADDI8 <fi#0>, 0; G8RC:%vreg276
>>>>> %vreg277<def> = LI8 0; G8RC:%vreg277
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg276; G8RC:%vreg276
>>>>> %X4<def> = COPY %vreg277; G8RC:%vreg277
>>>>> BL8_NOP <ga:@_ZNK4llvm5APInt13EqualSlowCaseEm>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X2<imp-use>, %R1<imp-def>, %X3<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg278<def> = COPY %X3; G8RC:%vreg278
>>>>> %vreg528<def> = ANDIo8 %vreg278, 1, %CR0<imp-def>; G8RC:%vreg528,%vreg278
>>>>> %vreg279<def> = COPY %CR0GT; CRBITRC:%vreg279
>>>>> BC %vreg279<kill>, <BB#112>; CRBITRC:%vreg279
>>>>> B <BB#53>
>>>>> Successors according to CFG: BB#112(0x40000000 / 0x80000000 = 50.00%) BB#53(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#53: derived from LLVM BB %if.end45
>>>>> Predecessors according to CFG: BB#52
>>>>> %vreg33<def> = LWZ 0, <fi#0>; mem:LD4[%50](align=8)(tbaa=!15) GPRC:%vreg33
>>>>> %vreg281<def> = IMPLICIT_DEF; G8RC:%vreg281
>>>>> %vreg280<def,tied1> = INSERT_SUBREG %vreg281<tied0>, %vreg30, sub_32; G8RC:%vreg280,%vreg281 GPRC_and_GPRC_NOR0:%vreg30
>>>>> %vreg34<def> = RLDICL %vreg280<kill>, 0, 32; G8RC:%vreg34,%vreg280
>>>>> %vreg282<def> = CMPLWI %vreg33, 64; CRRC:%vreg282 GPRC:%vreg33
>>>>> BCC 44, %vreg282<kill>, <BB#55>; CRRC:%vreg282
>>>>> B <BB#54>
>>>>> Successors according to CFG: BB#54(0x40000000 / 0x80000000 = 50.00%) BB#55(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#54: derived from LLVM BB %if.then.i.i.i.i
>>>>> Predecessors according to CFG: BB#53 BB#51
>>>>> %vreg35<def> = PHI %vreg34, <BB#53>, %vreg32, <BB#51>; G8RC:%vreg35,%vreg34,%vreg32
>>>>> %vreg36<def> = PHI %vreg33, <BB#53>, %vreg31, <BB#51>; GPRC:%vreg36,%vreg33,%vreg31
>>>>> %vreg289<def> = LD 8, <fi#0>; mem:LD8[%sunkaddr390](tbaa=!8) G8RC:%vreg289
>>>>> %vreg290<def> = SUBFIC %vreg36, 64, %CARRY<imp-def,dead>; GPRC:%vreg290,%vreg36
>>>>> %vreg291<def> = CNTLZD %vreg289<kill>; G8RC:%vreg291,%vreg289
>>>>> %vreg293<def> = IMPLICIT_DEF; G8RC:%vreg293
>>>>> %vreg292<def,tied1> = INSERT_SUBREG %vreg293<tied0>, %vreg290<kill>, sub_32; G8RC:%vreg292,%vreg293 GPRC:%vreg290
>>>>> %vreg294<def> = SUBF8 %vreg292<kill>, %vreg291<kill>; G8RC:%vreg294,%vreg292,%vreg291
>>>>> %vreg37<def> = COPY %vreg294:sub_32; GPRC:%vreg37 G8RC:%vreg294
>>>>> B <BB#56>
>>>>> Successors according to CFG: BB#56(?%)
>>>>>
>>>>> BB#55: derived from LLVM BB %if.end.i.i.i.i
>>>>> Predecessors according to CFG: BB#53
>>>>> %vreg283<def> = ADDI8 <fi#0>, 0; G8RC:%vreg283
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg283; G8RC:%vreg283
>>>>> BL8_NOP <ga:@_ZNK4llvm5APInt25countLeadingZerosSlowCaseEv>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X2<imp-use>, %R1<imp-def>, %X3<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg284<def> = COPY %X3; G8RC:%vreg284
>>>>> %vreg38<def> = COPY %vreg284:sub_32; GPRC:%vreg38 G8RC:%vreg284
>>>>> Successors according to CFG: BB#56(?%)
>>>>>
>>>>> BB#56: derived from LLVM BB %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i
>>>>> Predecessors according to CFG: BB#55 BB#54
>>>>> %vreg39<def> = PHI %vreg34, <BB#55>, %vreg35, <BB#54>; G8RC:%vreg39,%vreg34,%vreg35
>>>>> %vreg40<def> = PHI %vreg33, <BB#55>, %vreg36, <BB#54>; GPRC:%vreg40,%vreg33,%vreg36
>>>>> %vreg41<def> = PHI %vreg38, <BB#55>, %vreg37, <BB#54>; GPRC:%vreg41,%vreg38,%vreg37
>>>>> %vreg295<def> = SUBF %vreg41, %vreg40; GPRC:%vreg295,%vreg41,%vreg40
>>>>> %vreg296<def> = CMPLWI %vreg295<kill>, 64; CRRC:%vreg296 GPRC:%vreg295
>>>>> BCC 44, %vreg296<kill>, <BB#62>; CRRC:%vreg296
>>>>> B <BB#57>
>>>>> Successors according to CFG: BB#62(0x40000000 / 0x80000000 = 50.00%) BB#57(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#57: derived from LLVM BB %cond.false.i.i217
>>>>> Predecessors according to CFG: BB#56
>>>>> %vreg42<def> = LWZ 0, <fi#0>; mem:LD4[%55](align=8)(tbaa=!15) GPRC:%vreg42
>>>>> %vreg297<def> = CMPLWI %vreg42, 65; CRRC:%vreg297 GPRC:%vreg42
>>>>> BCC 4, %vreg297<kill>, <BB#58>; CRRC:%vreg297
>>>>> Successors according to CFG: BB#138(0x40000000 / 0x80000000 = 50.00%) BB#58(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#138:
>>>>> Predecessors according to CFG: BB#57
>>>>> %vreg9<def> = ADDI8 <fi#0>, 8; G8RC:%vreg9
>>>>> B <BB#61>
>>>>> Successors according to CFG: BB#61(?%)
>>>>>
>>>>> BB#58: derived from LLVM BB %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i.i
>>>>> Predecessors according to CFG: BB#57
>>>>> %vreg298<def> = ADDI8 <fi#0>, 0; G8RC:%vreg298
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg298; G8RC:%vreg298
>>>>> BL8_NOP <ga:@_ZNK4llvm5APInt25countLeadingZerosSlowCaseEv>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X2<imp-use>, %R1<imp-def>, %X3<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg299<def> = COPY %X3; G8RC:%vreg299
>>>>> %vreg300<def> = COPY %vreg299:sub_32; GPRC:%vreg300 G8RC:%vreg299
>>>>> %vreg301<def> = SUBF %vreg300<kill>, %vreg42; GPRC:%vreg301,%vreg300,%vreg42
>>>>> %vreg302<def> = CMPLWI %vreg301<kill>, 65; CRRC:%vreg302 GPRC:%vreg301
>>>>> BCC 15, %vreg302<kill>, <BB#60>; CRRC:%vreg302
>>>>> B <BB#59>
>>>>> Successors according to CFG: BB#60(0x7ffff800 / 0x80000000 = 100.00%) BB#59(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#59: derived from LLVM BB %cond.false.i.i.i
>>>>> Predecessors according to CFG: BB#58
>>>>> %vreg303<def> = ADDIStocHA %X2, <ga:@.str.91>; G8RC_and_G8RC_NOX0:%vreg303
>>>>> %vreg304<def> = LI8 1331; G8RC:%vreg304
>>>>> %vreg305<def> = ADDIStocHA %X2, <ga:@.str.74>; G8RC_and_G8RC_NOX0:%vreg305
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg306<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZNK4llvm5APInt12getZExtValueEv>; G8RC_and_G8RC_NOX0:%vreg306
>>>>> %vreg307<def> = ADDItocL %vreg303<kill>, <ga:@.str.91>; G8RC:%vreg307 G8RC_and_G8RC_NOX0:%vreg303
>>>>> %vreg308<def> = ADDItocL %vreg305<kill>, <ga:@.str.74>; G8RC:%vreg308 G8RC_and_G8RC_NOX0:%vreg305
>>>>> %vreg309<def> = ADDItocL %vreg306<kill>, <ga:@__PRETTY_FUNCTION__._ZNK4llvm5APInt12getZExtValueEv>; G8RC:%vreg309 G8RC_and_G8RC_NOX0:%vreg306
>>>>> %X3<def> = COPY %vreg307; G8RC:%vreg307
>>>>> %X4<def> = COPY %vreg308; G8RC:%vreg308
>>>>> %X5<def> = COPY %vreg304; G8RC:%vreg304
>>>>> %X6<def> = COPY %vreg309; G8RC:%vreg309
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#60: derived from LLVM BB %cond.end.i.i.i
>>>>> Predecessors according to CFG: BB#58
>>>>> %vreg43<def> = LD 8, <fi#0>; mem:LD8[%pVal.i.i.i](tbaa=!4) G8RC:%vreg43
>>>>> Successors according to CFG: BB#61(?%)
>>>>>
>>>>> BB#61: derived from LLVM BB %_ZNK4llvm5APInt3ugeEm.exit
>>>>> Predecessors according to CFG: BB#60 BB#138
>>>>> %vreg44<def> = PHI %vreg9, <BB#138>, %vreg43, <BB#60>; G8RC_and_G8RC_NOX0:%vreg44 G8RC:%vreg9,%vreg43
>>>>> %vreg310<def> = LD 0, %vreg44; mem:LD8[%retval.0.in.i.i.i](tbaa=!8) G8RC:%vreg310 G8RC_and_G8RC_NOX0:%vreg44
>>>>> %vreg311<def> = CMPLD %vreg310<kill>, %vreg39; CRRC:%vreg311 G8RC:%vreg310,%vreg39
>>>>> BCC 12, %vreg311<kill>, <BB#68>; CRRC:%vreg311
>>>>> B <BB#62>
>>>>> Successors according to CFG: BB#68(0x40000000 / 0x80000000 = 50.00%) BB#62(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#62: derived from LLVM BB %if.then47
>>>>> Predecessors according to CFG: BB#56 BB#61
>>>>> BCn %vreg2, <BB#64>; CRBITRC:%vreg2
>>>>> B <BB#63>
>>>>> Successors according to CFG: BB#63(0x40000000 / 0x80000000 = 50.00%) BB#64(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#63: derived from LLVM BB %if.then49
>>>>> Predecessors according to CFG: BB#62
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg26; G8RC_and_G8RC_NOX0:%vreg26
>>>>> BL8_NOP <ga:@_ZN4llvm21ConstantAggregateZero3getEPNS_4TypeE>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X2<imp-use>, %R1<imp-def>, %X3<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg482<def> = COPY %X3; G8RC:%vreg482
>>>>> %vreg45<def> = COPY %vreg482; G8RC:%vreg45,%vreg482
>>>>> B <BB#112>
>>>>> Successors according to CFG: BB#112(?%)
>>>>>
>>>>> BB#64: derived from LLVM BB %_ZN4llvm5APIntC2Ejmb.exit233
>>>>> Predecessors according to CFG: BB#62
>>>>> %vreg312<def> = ADDI %vreg30, -1; GPRC:%vreg312 GPRC_and_GPRC_NOR0:%vreg30
>>>>> %vreg313<def> = LWZ 0, <fi#0>; mem:LD4[%60](align=8)(tbaa=!15) GPRC:%vreg313
>>>>> %vreg315<def> = IMPLICIT_DEF; G8RC:%vreg315
>>>>> %vreg314<def,tied1> = INSERT_SUBREG %vreg315<tied0>, %vreg312<kill>, sub_32; G8RC:%vreg314,%vreg315 GPRC:%vreg312
>>>>> %vreg46<def> = RLDICL %vreg314<kill>, 0, 32; G8RC:%vreg46,%vreg314
>>>>> %vreg316<def> = CMPLWI %vreg313<kill>, 65; CRRC:%vreg316 GPRC:%vreg313
>>>>> BCC 12, %vreg316<kill>, <BB#67>; CRRC:%vreg316
>>>>> B <BB#65>
>>>>> Successors according to CFG: BB#67(0x40000000 / 0x80000000 = 50.00%) BB#65(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#65: derived from LLVM BB %if.then.i236
>>>>> Predecessors according to CFG: BB#64
>>>>> %vreg47<def> = LD 8, <fi#0>; mem:LD8[%pVal.i237](tbaa=!4) G8RC:%vreg47
>>>>> %vreg317<def> = CMPLDI %vreg47, 0; CRRC:%vreg317 G8RC:%vreg47
>>>>> BCC 76, %vreg317<kill>, <BB#67>; CRRC:%vreg317
>>>>> B <BB#66>
>>>>> Successors according to CFG: BB#67(0x30000000 / 0x80000000 = 37.50%) BB#66(0x50000000 / 0x80000000 = 62.50%)
>>>>>
>>>>> BB#66: derived from LLVM BB %delete.notnull.i240
>>>>> Predecessors according to CFG: BB#65
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg47; G8RC:%vreg47
>>>>> BL8_NOP <ga:@_ZdaPv>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> Successors according to CFG: BB#67(?%)
>>>>>
>>>>> BB#67: derived from LLVM BB %_ZN4llvm5APIntD2Ev.exit252
>>>>> Predecessors according to CFG: BB#64 BB#65 BB#66
>>>>> %vreg318<def> = LI 64; GPRC:%vreg318
>>>>> STD %vreg46, 8, <fi#0>; mem:ST8[%sunkaddr393] G8RC:%vreg46
>>>>> STW %vreg318<kill>, 0, <fi#0>; mem:ST4[%65](align=8)(tbaa=!15) GPRC:%vreg318
>>>>> Successors according to CFG: BB#68(?%)
>>>>>
>>>>> BB#68: derived from LLVM BB %if.end56
>>>>> Predecessors according to CFG: BB#61 BB#67
>>>>> %vreg320<def> = IMPLICIT_DEF; G8RC:%vreg320
>>>>> %vreg319<def,tied1> = INSERT_SUBREG %vreg320<tied0>, %vreg30, sub_32; G8RC:%vreg319,%vreg320 GPRC_and_GPRC_NOR0:%vreg30
>>>>> %vreg321<def> = RLDICL %vreg319<kill>, 0, 32; G8RC:%vreg321,%vreg319
>>>>> %vreg322<def> = ADDI8 <fi#3>, 0; G8RC:%vreg322
>>>>> %vreg323<def> = ADDI8 <fi#0>, 0; G8RC:%vreg323
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg322; G8RC:%vreg322
>>>>> %X4<def> = COPY %vreg323; G8RC:%vreg323
>>>>> %X5<def> = COPY %vreg321; G8RC:%vreg321
>>>>> BL8_NOP <ga:@_ZNK4llvm5APInt11zextOrTruncEj>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg28; G8RC:%vreg28
>>>>> %X4<def> = COPY %vreg322; G8RC:%vreg322
>>>>> BL8_NOP <ga:@_ZN4llvm11ConstantInt3getEPNS_4TypeERKNS_5APIntE>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X2<imp-use>, %R1<imp-def>, %X3<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg324<def> = COPY %X3; G8RC:%vreg324
>>>>> %vreg325<def> = LWZ 0, <fi#3>; mem:LD4[%BitWidth.i.i.i253394](align=8)(tbaa=!15) GPRC:%vreg325
>>>>> %vreg326<def> = CMPLWI %vreg325<kill>, 65; CRRC:%vreg326 GPRC:%vreg325
>>>>> BCC 12, %vreg326<kill>, <BB#71>; CRRC:%vreg326
>>>>> B <BB#69>
>>>>> Successors according to CFG: BB#69(0x40000000 / 0x80000000 = 50.00%) BB#71(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#69: derived from LLVM BB %if.then.i257
>>>>> Predecessors according to CFG: BB#68
>>>>> %vreg49<def> = LD 8, <fi#3>; mem:LD8[%pVal.i255](tbaa=!4) G8RC:%vreg49
>>>>> %vreg327<def> = CMPLDI %vreg49, 0; CRRC:%vreg327 G8RC:%vreg49
>>>>> BCC 76, %vreg327<kill>, <BB#71>; CRRC:%vreg327
>>>>> B <BB#70>
>>>>> Successors according to CFG: BB#71(0x30000000 / 0x80000000 = 37.50%) BB#70(0x50000000 / 0x80000000 = 62.50%)
>>>>>
>>>>> BB#70: derived from LLVM BB %delete.notnull.i258
>>>>> Predecessors according to CFG: BB#69
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg49; G8RC:%vreg49
>>>>> BL8_NOP <ga:@_ZdaPv>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> Successors according to CFG: BB#71(?%)
>>>>>
>>>>> BB#71: derived from LLVM BB %_ZN4llvm5APIntD2Ev.exit260
>>>>> Predecessors according to CFG: BB#68 BB#69 BB#70
>>>>> %vreg50<def> = LI 257; GPRC:%vreg50
>>>>> %vreg51<def> = LI 1; GPRC:%vreg51
>>>>> %vreg328<def> = CRUNSET; CRBITRC:%vreg328
>>>>> STH %vreg50, 16, <fi#4>; mem:ST2[%70](align=8) GPRC:%vreg50
>>>>> BC %vreg328, <BB#73>; CRBITRC:%vreg328
>>>>> B <BB#72>
>>>>> Successors according to CFG: BB#72(0x40000000 / 0x80000000 = 50.00%) BB#73(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#72: derived from LLVM BB %land.lhs.true.i.i
>>>>> Predecessors according to CFG: BB#71
>>>>> %vreg335<def> = RLWINM %vreg50, 0, 24, 31; GPRC:%vreg335,%vreg50
>>>>> %vreg336<def> = CMPLWI %vreg335<kill>, 1; CRRC:%vreg336 GPRC:%vreg335
>>>>> BCC 79, %vreg336<kill>, <BB#75>; CRRC:%vreg336
>>>>> B <BB#79>
>>>>> Successors according to CFG: BB#75(0x7ffff800 / 0x80000000 = 100.00%) BB#79(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#73: derived from LLVM BB %if.end.i.i
>>>>> Predecessors according to CFG: BB#71
>>>>> %vreg329<def> = RLWINM %vreg50, 0, 24, 31; GPRC:%vreg329,%vreg50
>>>>> %vreg330<def> = CMPLWI %vreg329, 1; CRRC:%vreg330 GPRC:%vreg329
>>>>> BCC 76, %vreg330<kill>, <BB#75>; CRRC:%vreg330
>>>>> B <BB#124>
>>>>> Successors according to CFG: BB#75(0x3ffffc00 / 0x80000000 = 50.00%) BB#124(0x40000400 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#124: derived from LLVM BB %if.end.i.i
>>>>> Predecessors according to CFG: BB#73
>>>>> %vreg331<def> = CMPLWI %vreg329, 0; CRRC:%vreg331 GPRC:%vreg329
>>>>> BCC 76, %vreg331<kill>, <BB#79>; CRRC:%vreg331
>>>>> B <BB#74>
>>>>> Successors according to CFG: BB#79(0x00001000 / 0x80000000 = 0.00%) BB#74(0x7ffff000 / 0x80000000 = 100.00%)
>>>>>
>>>>> BB#74: derived from LLVM BB %land.lhs.true11.i.i
>>>>> Predecessors according to CFG: BB#124
>>>>> %vreg333<def> = CMPLWI %vreg51, 2; CRRC:%vreg333 GPRC:%vreg51
>>>>> BCC 76, %vreg333<kill>, <BB#76>; CRRC:%vreg333
>>>>> B <BB#125>
>>>>> Successors according to CFG: BB#76(0x3ffffc00 / 0x80000000 = 50.00%) BB#125(0x40000400 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#125: derived from LLVM BB %land.lhs.true11.i.i
>>>>> Predecessors according to CFG: BB#74
>>>>> %vreg334<def> = CMPLWI %vreg51, 0; CRRC:%vreg334 GPRC:%vreg51
>>>>> BCC 68, %vreg334<kill>, <BB#79>; CRRC:%vreg334
>>>>> B <BB#77>
>>>>> Successors according to CFG: BB#79(0x00001000 / 0x80000000 = 0.00%) BB#77(0x7ffff000 / 0x80000000 = 100.00%)
>>>>>
>>>>> BB#75: derived from LLVM BB %if.end16.i.i
>>>>> Predecessors according to CFG: BB#73 BB#72
>>>>> %vreg337<def> = CMPLWI %vreg51, 2; CRRC:%vreg337 GPRC:%vreg51
>>>>> BCC 68, %vreg337<kill>, <BB#80>; CRRC:%vreg337
>>>>> B <BB#76>
>>>>> Successors according to CFG: BB#76(0x40000000 / 0x80000000 = 50.00%) BB#80(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#76: derived from LLVM BB %land.lhs.true20.i.i
>>>>> Predecessors according to CFG: BB#74 BB#75
>>>>> %vreg338<def> = LD 0, <fi#4>; mem:LD8[%twine.i.i395](tbaa=!4) G8RC_and_G8RC_NOX0:%vreg338
>>>>> %vreg339<def> = LHZ 16, %vreg338<kill>; mem:LD2[%84](align=8) GPRC:%vreg339 G8RC_and_G8RC_NOX0:%vreg338
>>>>> %vreg340<def> = RLWINM %vreg339, 0, 24, 31; GPRC:%vreg340,%vreg339
>>>>> %vreg341<def> = CMPLWI %vreg339, 256; CRRC:%vreg341 GPRC:%vreg339
>>>>> %vreg342<def> = CMPWI %vreg340<kill>, 1; CRRC:%vreg342 GPRC:%vreg340
>>>>> %vreg343<def> = COPY %vreg341:sub_lt; CRBITRC:%vreg343 CRRC:%vreg341
>>>>> %vreg344<def> = COPY %vreg342:sub_eq; CRBITRC:%vreg344 CRRC:%vreg342
>>>>> %vreg345<def> = CROR %vreg343<kill>, %vreg344<kill>; CRBITRC:%vreg345,%vreg343,%vreg344
>>>>> BC %vreg345<kill>, <BB#79>; CRBITRC:%vreg345
>>>>> B <BB#77>
>>>>> Successors according to CFG: BB#77(0x7ffff800 / 0x80000000 = 100.00%) BB#79(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#77: derived from LLVM BB %if.end23.i.i
>>>>> Predecessors according to CFG: BB#125 BB#76
>>>>> %vreg346<def> = RLWINM %vreg50, 0, 24, 31; GPRC:%vreg346,%vreg50
>>>>> %vreg347<def> = CMPLWI %vreg346<kill>, 2; CRRC:%vreg347 GPRC:%vreg346
>>>>> BCC 68, %vreg347<kill>, <BB#80>; CRRC:%vreg347
>>>>> B <BB#78>
>>>>> Successors according to CFG: BB#78(0x40000000 / 0x80000000 = 50.00%) BB#80(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#78: derived from LLVM BB %land.lhs.true27.i.i
>>>>> Predecessors according to CFG: BB#77
>>>>> %vreg348<def> = LD 8, <fi#4>; mem:LD8[%twine28.i.i](tbaa=!4) G8RC_and_G8RC_NOX0:%vreg348
>>>>> %vreg349<def> = LHZ 16, %vreg348<kill>; mem:LD2[%90](align=8) GPRC:%vreg349 G8RC_and_G8RC_NOX0:%vreg348
>>>>> %vreg350<def> = RLWINM %vreg349, 0, 24, 31; GPRC:%vreg350,%vreg349
>>>>> %vreg351<def> = CMPLWI %vreg349, 255; CRRC:%vreg351 GPRC:%vreg349
>>>>> %vreg352<def> = CMPWI %vreg350<kill>, 1; CRRC:%vreg352 GPRC:%vreg350
>>>>> %vreg353<def> = COPY %vreg351:sub_gt; CRBITRC:%vreg353 CRRC:%vreg351
>>>>> %vreg354<def> = COPY %vreg352:sub_eq; CRBITRC:%vreg354 CRRC:%vreg352
>>>>> %vreg355<def> = CRANDC %vreg353<kill>, %vreg354<kill>; CRBITRC:%vreg355,%vreg353,%vreg354
>>>>> BC %vreg355<kill>, <BB#80>; CRBITRC:%vreg355
>>>>> B <BB#79>
>>>>> Successors according to CFG: BB#80(0x7ffff800 / 0x80000000 = 100.00%) BB#79(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#79: derived from LLVM BB %cond.false.i263
>>>>> Predecessors according to CFG: BB#124 BB#125 BB#72 BB#76 BB#78
>>>>> %vreg356<def> = ADDIStocHA %X2, <ga:@.str.36>; G8RC_and_G8RC_NOX0:%vreg356
>>>>> %vreg357<def> = LI8 274; G8RC:%vreg357
>>>>> %vreg358<def> = ADDIStocHA %X2, <ga:@.str.37>; G8RC_and_G8RC_NOX0:%vreg358
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg359<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZN4llvm5TwineC2EPKc>; G8RC_and_G8RC_NOX0:%vreg359
>>>>> %vreg360<def> = ADDItocL %vreg356<kill>, <ga:@.str.36>; G8RC:%vreg360 G8RC_and_G8RC_NOX0:%vreg356
>>>>> %vreg361<def> = ADDItocL %vreg358<kill>, <ga:@.str.37>; G8RC:%vreg361 G8RC_and_G8RC_NOX0:%vreg358
>>>>> %vreg362<def> = ADDItocL %vreg359<kill>, <ga:@__PRETTY_FUNCTION__._ZN4llvm5TwineC2EPKc>; G8RC:%vreg362 G8RC_and_G8RC_NOX0:%vreg359
>>>>> %X3<def> = COPY %vreg360; G8RC:%vreg360
>>>>> %X4<def> = COPY %vreg361; G8RC:%vreg361
>>>>> %X5<def> = COPY %vreg357; G8RC:%vreg357
>>>>> %X6<def> = COPY %vreg362; G8RC:%vreg362
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#80: derived from LLVM BB %_ZN4llvm5TwineC2EPKc.exit
>>>>> Predecessors according to CFG: BB#75 BB#77 BB#78
>>>>> %vreg48<def> = COPY %vreg324; G8RC:%vreg48,%vreg324
>>>>> %vreg364<def> = IMPLICIT_DEF; G8RC:%vreg364
>>>>> %vreg363<def,tied1> = INSERT_SUBREG %vreg364<tied0>, %vreg29, sub_32; G8RC:%vreg363,%vreg364 GPRC:%vreg29
>>>>> %vreg365<def> = RLDICL %vreg363<kill>, 0, 32; G8RC:%vreg365,%vreg363
>>>>> %vreg366<def> = ADDI8 <fi#4>, 0; G8RC:%vreg366
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg66; G8RC:%vreg66
>>>>> %X4<def> = COPY %vreg365; G8RC:%vreg365
>>>>> %X5<def> = COPY %vreg48; G8RC:%vreg48
>>>>> %X6<def> = COPY %vreg366; G8RC:%vreg366
>>>>> BL8_NOP <ga:@_ZN4llvm9IRBuilderILb1ENS_12TargetFolderENS_21InstCombineIRInserterEE17CreateVectorSplatEjPNS_5ValueERKNS_5TwineE>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>, %X3<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg367<def> = COPY %X3; G8RC:%vreg367
>>>>> %vreg52<def> = COPY %vreg367; G8RC:%vreg52,%vreg367
>>>>> BCn %vreg1, <BB#91>; CRBITRC:%vreg1
>>>>> B <BB#81>
>>>>> Successors according to CFG: BB#81(0x40000000 / 0x80000000 = 50.00%) BB#91(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#81: derived from LLVM BB %if.then62
>>>>> Predecessors according to CFG: BB#80
>>>>> %vreg53<def> = LI 257; GPRC:%vreg53
>>>>> %vreg54<def> = LI 1; GPRC:%vreg54
>>>>> STH %vreg53, 16, <fi#5>; mem:ST2[%95](align=8) GPRC:%vreg53
>>>>> BC %vreg328, <BB#83>; CRBITRC:%vreg328
>>>>> B <BB#82>
>>>>> Successors according to CFG: BB#82(0x40000000 / 0x80000000 = 50.00%) BB#83(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#82: derived from LLVM BB %land.lhs.true.i.i268
>>>>> Predecessors according to CFG: BB#81
>>>>> %vreg451<def> = RLWINM %vreg53, 0, 24, 31; GPRC:%vreg451,%vreg53
>>>>> %vreg452<def> = CMPLWI %vreg451<kill>, 1; CRRC:%vreg452 GPRC:%vreg451
>>>>> BCC 79, %vreg452<kill>, <BB#85>; CRRC:%vreg452
>>>>> B <BB#89>
>>>>> Successors according to CFG: BB#85(0x7ffff800 / 0x80000000 = 100.00%) BB#89(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#83: derived from LLVM BB %if.end.i.i269
>>>>> Predecessors according to CFG: BB#81
>>>>> %vreg445<def> = RLWINM %vreg53, 0, 24, 31; GPRC:%vreg445,%vreg53
>>>>> %vreg446<def> = CMPLWI %vreg445, 1; CRRC:%vreg446 GPRC:%vreg445
>>>>> BCC 76, %vreg446<kill>, <BB#85>; CRRC:%vreg446
>>>>> B <BB#130>
>>>>> Successors according to CFG: BB#85(0x3ffffc00 / 0x80000000 = 50.00%) BB#130(0x40000400 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#130: derived from LLVM BB %if.end.i.i269
>>>>> Predecessors according to CFG: BB#83
>>>>> %vreg447<def> = CMPLWI %vreg445, 0; CRRC:%vreg447 GPRC:%vreg445
>>>>> BCC 76, %vreg447<kill>, <BB#89>; CRRC:%vreg447
>>>>> B <BB#84>
>>>>> Successors according to CFG: BB#89(0x00001000 / 0x80000000 = 0.00%) BB#84(0x7ffff000 / 0x80000000 = 100.00%)
>>>>>
>>>>> BB#84: derived from LLVM BB %land.lhs.true11.i.i270
>>>>> Predecessors according to CFG: BB#130
>>>>> %vreg449<def> = CMPLWI %vreg54, 2; CRRC:%vreg449 GPRC:%vreg54
>>>>> BCC 76, %vreg449<kill>, <BB#86>; CRRC:%vreg449
>>>>> B <BB#131>
>>>>> Successors according to CFG: BB#86(0x3ffffc00 / 0x80000000 = 50.00%) BB#131(0x40000400 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#131: derived from LLVM BB %land.lhs.true11.i.i270
>>>>> Predecessors according to CFG: BB#84
>>>>> %vreg450<def> = CMPLWI %vreg54, 0; CRRC:%vreg450 GPRC:%vreg54
>>>>> BCC 68, %vreg450<kill>, <BB#89>; CRRC:%vreg450
>>>>> B <BB#87>
>>>>> Successors according to CFG: BB#89(0x00001000 / 0x80000000 = 0.00%) BB#87(0x7ffff000 / 0x80000000 = 100.00%)
>>>>>
>>>>> BB#85: derived from LLVM BB %if.end16.i.i272
>>>>> Predecessors according to CFG: BB#83 BB#82
>>>>> %vreg453<def> = CMPLWI %vreg54, 2; CRRC:%vreg453 GPRC:%vreg54
>>>>> BCC 68, %vreg453<kill>, <BB#90>; CRRC:%vreg453
>>>>> B <BB#86>
>>>>> Successors according to CFG: BB#86(0x40000000 / 0x80000000 = 50.00%) BB#90(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#86: derived from LLVM BB %land.lhs.true20.i.i277
>>>>> Predecessors according to CFG: BB#84 BB#85
>>>>> %vreg454<def> = LD 0, <fi#5>; mem:LD8[%twine.i.i273396](tbaa=!4) G8RC_and_G8RC_NOX0:%vreg454
>>>>> %vreg455<def> = LHZ 16, %vreg454<kill>; mem:LD2[%109](align=8) GPRC:%vreg455 G8RC_and_G8RC_NOX0:%vreg454
>>>>> %vreg456<def> = RLWINM %vreg455, 0, 24, 31; GPRC:%vreg456,%vreg455
>>>>> %vreg457<def> = CMPLWI %vreg455, 256; CRRC:%vreg457 GPRC:%vreg455
>>>>> %vreg458<def> = CMPWI %vreg456<kill>, 1; CRRC:%vreg458 GPRC:%vreg456
>>>>> %vreg459<def> = COPY %vreg457:sub_lt; CRBITRC:%vreg459 CRRC:%vreg457
>>>>> %vreg460<def> = COPY %vreg458:sub_eq; CRBITRC:%vreg460 CRRC:%vreg458
>>>>> %vreg461<def> = CROR %vreg459<kill>, %vreg460<kill>; CRBITRC:%vreg461,%vreg459,%vreg460
>>>>> BC %vreg461<kill>, <BB#89>; CRBITRC:%vreg461
>>>>> B <BB#87>
>>>>> Successors according to CFG: BB#87(0x7ffff800 / 0x80000000 = 100.00%) BB#89(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#87: derived from LLVM BB %if.end23.i.i279
>>>>> Predecessors according to CFG: BB#131 BB#86
>>>>> %vreg462<def> = RLWINM %vreg53, 0, 24, 31; GPRC:%vreg462,%vreg53
>>>>> %vreg463<def> = CMPLWI %vreg462<kill>, 2; CRRC:%vreg463 GPRC:%vreg462
>>>>> BCC 68, %vreg463<kill>, <BB#90>; CRRC:%vreg463
>>>>> B <BB#88>
>>>>> Successors according to CFG: BB#88(0x40000000 / 0x80000000 = 50.00%) BB#90(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#88: derived from LLVM BB %land.lhs.true27.i.i284
>>>>> Predecessors according to CFG: BB#87
>>>>> %vreg464<def> = LD 8, <fi#5>; mem:LD8[%twine28.i.i280](tbaa=!4) G8RC_and_G8RC_NOX0:%vreg464
>>>>> %vreg465<def> = LHZ 16, %vreg464<kill>; mem:LD2[%115](align=8) GPRC:%vreg465 G8RC_and_G8RC_NOX0:%vreg464
>>>>> %vreg466<def> = RLWINM %vreg465, 0, 24, 31; GPRC:%vreg466,%vreg465
>>>>> %vreg467<def> = CMPLWI %vreg465, 255; CRRC:%vreg467 GPRC:%vreg465
>>>>> %vreg468<def> = CMPWI %vreg466<kill>, 1; CRRC:%vreg468 GPRC:%vreg466
>>>>> %vreg469<def> = COPY %vreg467:sub_gt; CRBITRC:%vreg469 CRRC:%vreg467
>>>>> %vreg470<def> = COPY %vreg468:sub_eq; CRBITRC:%vreg470 CRRC:%vreg468
>>>>> %vreg471<def> = CRANDC %vreg469<kill>, %vreg470<kill>; CRBITRC:%vreg471,%vreg469,%vreg470
>>>>> BC %vreg471<kill>, <BB#90>; CRBITRC:%vreg471
>>>>> B <BB#89>
>>>>> Successors according to CFG: BB#90(0x7ffff800 / 0x80000000 = 100.00%) BB#89(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#89: derived from LLVM BB %cond.false.i285
>>>>> Predecessors according to CFG: BB#130 BB#131 BB#82 BB#86 BB#88
>>>>> %vreg472<def> = ADDIStocHA %X2, <ga:@.str.36>; G8RC_and_G8RC_NOX0:%vreg472
>>>>> %vreg473<def> = LI8 274; G8RC:%vreg473
>>>>> %vreg474<def> = ADDIStocHA %X2, <ga:@.str.37>; G8RC_and_G8RC_NOX0:%vreg474
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg475<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZN4llvm5TwineC2EPKc>; G8RC_and_G8RC_NOX0:%vreg475
>>>>> %vreg476<def> = ADDItocL %vreg472<kill>, <ga:@.str.36>; G8RC:%vreg476 G8RC_and_G8RC_NOX0:%vreg472
>>>>> %vreg477<def> = ADDItocL %vreg474<kill>, <ga:@.str.37>; G8RC:%vreg477 G8RC_and_G8RC_NOX0:%vreg474
>>>>> %vreg478<def> = ADDItocL %vreg475<kill>, <ga:@__PRETTY_FUNCTION__._ZN4llvm5TwineC2EPKc>; G8RC:%vreg478 G8RC_and_G8RC_NOX0:%vreg475
>>>>> %X3<def> = COPY %vreg476; G8RC:%vreg476
>>>>> %X4<def> = COPY %vreg477; G8RC:%vreg477
>>>>> %X5<def> = COPY %vreg473; G8RC:%vreg473
>>>>> %X6<def> = COPY %vreg478; G8RC:%vreg478
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#90: derived from LLVM BB %_ZN4llvm5TwineC2EPKc.exit287
>>>>> Predecessors according to CFG: BB#85 BB#87 BB#88
>>>>> %vreg479<def> = ADDI8 <fi#5>, 0; G8RC:%vreg479
>>>>> %vreg480<def> = LI8 0; G8RC:%vreg480
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg66; G8RC:%vreg66
>>>>> %X4<def> = COPY %vreg25; G8RC_and_G8RC_NOX0:%vreg25
>>>>> %X5<def> = COPY %vreg52; G8RC:%vreg52
>>>>> %X6<def> = COPY %vreg479; G8RC:%vreg479
>>>>> %X7<def> = COPY %vreg480; G8RC:%vreg480
>>>>> %X8<def> = COPY %vreg480; G8RC:%vreg480
>>>>> BL8_NOP <ga:@_ZN4llvm9IRBuilderILb1ENS_12TargetFolderENS_21InstCombineIRInserterEE9CreateShlEPNS_5ValueES5_RKNS_5TwineEbb>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X7<imp-use>, %X8<imp-use>, %X2<imp-use>, %R1<imp-def>, %X3<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg481<def> = COPY %X3; G8RC:%vreg481
>>>>> %vreg55<def> = COPY %vreg481; G8RC:%vreg55,%vreg481
>>>>> B <BB#112>
>>>>> Successors according to CFG: BB#112(?%)
>>>>>
>>>>> BB#91: derived from LLVM BB %if.end65
>>>>> Predecessors according to CFG: BB#80
>>>>> BCn %vreg2, <BB#102>; CRBITRC:%vreg2
>>>>> B <BB#92>
>>>>> Successors according to CFG: BB#92(0x40000000 / 0x80000000 = 50.00%) BB#102(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#92: derived from LLVM BB %if.then67
>>>>> Predecessors according to CFG: BB#91
>>>>> %vreg56<def> = LI 257; GPRC:%vreg56
>>>>> %vreg57<def> = LI 1; GPRC:%vreg57
>>>>> STH %vreg56, 16, <fi#6>; mem:ST2[%119](align=8) GPRC:%vreg56
>>>>> BC %vreg328, <BB#94>; CRBITRC:%vreg328
>>>>> B <BB#93>
>>>>> Successors according to CFG: BB#93(0x40000000 / 0x80000000 = 50.00%) BB#94(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#93: derived from LLVM BB %land.lhs.true.i.i291
>>>>> Predecessors according to CFG: BB#92
>>>>> %vreg413<def> = RLWINM %vreg56, 0, 24, 31; GPRC:%vreg413,%vreg56
>>>>> %vreg414<def> = CMPLWI %vreg413<kill>, 1; CRRC:%vreg414 GPRC:%vreg413
>>>>> BCC 79, %vreg414<kill>, <BB#96>; CRRC:%vreg414
>>>>> B <BB#100>
>>>>> Successors according to CFG: BB#96(0x7ffff800 / 0x80000000 = 100.00%) BB#100(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#94: derived from LLVM BB %if.end.i.i292
>>>>> Predecessors according to CFG: BB#92
>>>>> %vreg407<def> = RLWINM %vreg56, 0, 24, 31; GPRC:%vreg407,%vreg56
>>>>> %vreg408<def> = CMPLWI %vreg407, 1; CRRC:%vreg408 GPRC:%vreg407
>>>>> BCC 76, %vreg408<kill>, <BB#96>; CRRC:%vreg408
>>>>> B <BB#128>
>>>>> Successors according to CFG: BB#96(0x3ffffc00 / 0x80000000 = 50.00%) BB#128(0x40000400 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#128: derived from LLVM BB %if.end.i.i292
>>>>> Predecessors according to CFG: BB#94
>>>>> %vreg409<def> = CMPLWI %vreg407, 0; CRRC:%vreg409 GPRC:%vreg407
>>>>> BCC 76, %vreg409<kill>, <BB#100>; CRRC:%vreg409
>>>>> B <BB#95>
>>>>> Successors according to CFG: BB#100(0x00001000 / 0x80000000 = 0.00%) BB#95(0x7ffff000 / 0x80000000 = 100.00%)
>>>>>
>>>>> BB#95: derived from LLVM BB %land.lhs.true11.i.i293
>>>>> Predecessors according to CFG: BB#128
>>>>> %vreg411<def> = CMPLWI %vreg57, 2; CRRC:%vreg411 GPRC:%vreg57
>>>>> BCC 76, %vreg411<kill>, <BB#97>; CRRC:%vreg411
>>>>> B <BB#129>
>>>>> Successors according to CFG: BB#97(0x3ffffc00 / 0x80000000 = 50.00%) BB#129(0x40000400 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#129: derived from LLVM BB %land.lhs.true11.i.i293
>>>>> Predecessors according to CFG: BB#95
>>>>> %vreg412<def> = CMPLWI %vreg57, 0; CRRC:%vreg412 GPRC:%vreg57
>>>>> BCC 68, %vreg412<kill>, <BB#100>; CRRC:%vreg412
>>>>> B <BB#98>
>>>>> Successors according to CFG: BB#100(0x00001000 / 0x80000000 = 0.00%) BB#98(0x7ffff000 / 0x80000000 = 100.00%)
>>>>>
>>>>> BB#96: derived from LLVM BB %if.end16.i.i295
>>>>> Predecessors according to CFG: BB#94 BB#93
>>>>> %vreg415<def> = CMPLWI %vreg57, 2; CRRC:%vreg415 GPRC:%vreg57
>>>>> BCC 68, %vreg415<kill>, <BB#101>; CRRC:%vreg415
>>>>> B <BB#97>
>>>>> Successors according to CFG: BB#97(0x40000000 / 0x80000000 = 50.00%) BB#101(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#97: derived from LLVM BB %land.lhs.true20.i.i300
>>>>> Predecessors according to CFG: BB#95 BB#96
>>>>> %vreg416<def> = LD 0, <fi#6>; mem:LD8[%twine.i.i296397](tbaa=!4) G8RC_and_G8RC_NOX0:%vreg416
>>>>> %vreg417<def> = LHZ 16, %vreg416<kill>; mem:LD2[%133](align=8) GPRC:%vreg417 G8RC_and_G8RC_NOX0:%vreg416
>>>>> %vreg418<def> = RLWINM %vreg417, 0, 24, 31; GPRC:%vreg418,%vreg417
>>>>> %vreg419<def> = CMPLWI %vreg417, 256; CRRC:%vreg419 GPRC:%vreg417
>>>>> %vreg420<def> = CMPWI %vreg418<kill>, 1; CRRC:%vreg420 GPRC:%vreg418
>>>>> %vreg421<def> = COPY %vreg419:sub_lt; CRBITRC:%vreg421 CRRC:%vreg419
>>>>> %vreg422<def> = COPY %vreg420:sub_eq; CRBITRC:%vreg422 CRRC:%vreg420
>>>>> %vreg423<def> = CROR %vreg421<kill>, %vreg422<kill>; CRBITRC:%vreg423,%vreg421,%vreg422
>>>>> BC %vreg423<kill>, <BB#100>; CRBITRC:%vreg423
>>>>> B <BB#98>
>>>>> Successors according to CFG: BB#98(0x7ffff800 / 0x80000000 = 100.00%) BB#100(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#98: derived from LLVM BB %if.end23.i.i302
>>>>> Predecessors according to CFG: BB#129 BB#97
>>>>> %vreg424<def> = RLWINM %vreg56, 0, 24, 31; GPRC:%vreg424,%vreg56
>>>>> %vreg425<def> = CMPLWI %vreg424<kill>, 2; CRRC:%vreg425 GPRC:%vreg424
>>>>> BCC 68, %vreg425<kill>, <BB#101>; CRRC:%vreg425
>>>>> B <BB#99>
>>>>> Successors according to CFG: BB#99(0x40000000 / 0x80000000 = 50.00%) BB#101(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#99: derived from LLVM BB %land.lhs.true27.i.i307
>>>>> Predecessors according to CFG: BB#98
>>>>> %vreg426<def> = LD 8, <fi#6>; mem:LD8[%twine28.i.i303](tbaa=!4) G8RC_and_G8RC_NOX0:%vreg426
>>>>> %vreg427<def> = LHZ 16, %vreg426<kill>; mem:LD2[%139](align=8) GPRC:%vreg427 G8RC_and_G8RC_NOX0:%vreg426
>>>>> %vreg428<def> = RLWINM %vreg427, 0, 24, 31; GPRC:%vreg428,%vreg427
>>>>> %vreg429<def> = CMPLWI %vreg427, 255; CRRC:%vreg429 GPRC:%vreg427
>>>>> %vreg430<def> = CMPWI %vreg428<kill>, 1; CRRC:%vreg430 GPRC:%vreg428
>>>>> %vreg431<def> = COPY %vreg429:sub_gt; CRBITRC:%vreg431 CRRC:%vreg429
>>>>> %vreg432<def> = COPY %vreg430:sub_eq; CRBITRC:%vreg432 CRRC:%vreg430
>>>>> %vreg433<def> = CRANDC %vreg431<kill>, %vreg432<kill>; CRBITRC:%vreg433,%vreg431,%vreg432
>>>>> BC %vreg433<kill>, <BB#101>; CRBITRC:%vreg433
>>>>> B <BB#100>
>>>>> Successors according to CFG: BB#101(0x7ffff800 / 0x80000000 = 100.00%) BB#100(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#100: derived from LLVM BB %cond.false.i308
>>>>> Predecessors according to CFG: BB#128 BB#129 BB#93 BB#97 BB#99
>>>>> %vreg434<def> = ADDIStocHA %X2, <ga:@.str.36>; G8RC_and_G8RC_NOX0:%vreg434
>>>>> %vreg435<def> = LI8 274; G8RC:%vreg435
>>>>> %vreg436<def> = ADDIStocHA %X2, <ga:@.str.37>; G8RC_and_G8RC_NOX0:%vreg436
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg437<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZN4llvm5TwineC2EPKc>; G8RC_and_G8RC_NOX0:%vreg437
>>>>> %vreg438<def> = ADDItocL %vreg434<kill>, <ga:@.str.36>; G8RC:%vreg438 G8RC_and_G8RC_NOX0:%vreg434
>>>>> %vreg439<def> = ADDItocL %vreg436<kill>, <ga:@.str.37>; G8RC:%vreg439 G8RC_and_G8RC_NOX0:%vreg436
>>>>> %vreg440<def> = ADDItocL %vreg437<kill>, <ga:@__PRETTY_FUNCTION__._ZN4llvm5TwineC2EPKc>; G8RC:%vreg440 G8RC_and_G8RC_NOX0:%vreg437
>>>>> %X3<def> = COPY %vreg438; G8RC:%vreg438
>>>>> %X4<def> = COPY %vreg439; G8RC:%vreg439
>>>>> %X5<def> = COPY %vreg435; G8RC:%vreg435
>>>>> %X6<def> = COPY %vreg440; G8RC:%vreg440
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#101: derived from LLVM BB %_ZN4llvm5TwineC2EPKc.exit310
>>>>> Predecessors according to CFG: BB#96 BB#98 BB#99
>>>>> %vreg441<def> = ADDI8 <fi#6>, 0; G8RC:%vreg441
>>>>> %vreg442<def> = LI8 0; G8RC:%vreg442
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg66; G8RC:%vreg66
>>>>> %X4<def> = COPY %vreg25; G8RC_and_G8RC_NOX0:%vreg25
>>>>> %X5<def> = COPY %vreg52; G8RC:%vreg52
>>>>> %X6<def> = COPY %vreg441; G8RC:%vreg441
>>>>> %X7<def> = COPY %vreg442; G8RC:%vreg442
>>>>> BL8_NOP <ga:@_ZN4llvm9IRBuilderILb1ENS_12TargetFolderENS_21InstCombineIRInserterEE10CreateLShrEPNS_5ValueES5_RKNS_5TwineEb>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X7<imp-use>, %X2<imp-use>, %R1<imp-def>, %X3<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg443<def> = COPY %X3; G8RC:%vreg443
>>>>> %vreg58<def> = COPY %vreg443; G8RC:%vreg58,%vreg443
>>>>> B <BB#112>
>>>>> Successors according to CFG: BB#112(?%)
>>>>>
>>>>> BB#102: derived from LLVM BB %if.end70
>>>>> Predecessors according to CFG: BB#91
>>>>> %vreg59<def> = LI 257; GPRC:%vreg59
>>>>> %vreg60<def> = LI 1; GPRC:%vreg60
>>>>> STH %vreg59, 16, <fi#7>; mem:ST2[%143](align=8) GPRC:%vreg59
>>>>> BC %vreg328, <BB#104>; CRBITRC:%vreg328
>>>>> B <BB#103>
>>>>> Successors according to CFG: BB#103(0x40000000 / 0x80000000 = 50.00%) BB#104(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#103: derived from LLVM BB %land.lhs.true.i.i314
>>>>> Predecessors according to CFG: BB#102
>>>>> %vreg375<def> = RLWINM %vreg59, 0, 24, 31; GPRC:%vreg375,%vreg59
>>>>> %vreg376<def> = CMPLWI %vreg375<kill>, 1; CRRC:%vreg376 GPRC:%vreg375
>>>>> BCC 79, %vreg376<kill>, <BB#106>; CRRC:%vreg376
>>>>> B <BB#110>
>>>>> Successors according to CFG: BB#106(0x7ffff800 / 0x80000000 = 100.00%) BB#110(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#104: derived from LLVM BB %if.end.i.i315
>>>>> Predecessors according to CFG: BB#102
>>>>> %vreg369<def> = RLWINM %vreg59, 0, 24, 31; GPRC:%vreg369,%vreg59
>>>>> %vreg370<def> = CMPLWI %vreg369, 1; CRRC:%vreg370 GPRC:%vreg369
>>>>> BCC 76, %vreg370<kill>, <BB#106>; CRRC:%vreg370
>>>>> B <BB#126>
>>>>> Successors according to CFG: BB#106(0x3ffffc00 / 0x80000000 = 50.00%) BB#126(0x40000400 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#126: derived from LLVM BB %if.end.i.i315
>>>>> Predecessors according to CFG: BB#104
>>>>> %vreg371<def> = CMPLWI %vreg369, 0; CRRC:%vreg371 GPRC:%vreg369
>>>>> BCC 76, %vreg371<kill>, <BB#110>; CRRC:%vreg371
>>>>> B <BB#105>
>>>>> Successors according to CFG: BB#110(0x00001000 / 0x80000000 = 0.00%) BB#105(0x7ffff000 / 0x80000000 = 100.00%)
>>>>>
>>>>> BB#105: derived from LLVM BB %land.lhs.true11.i.i316
>>>>> Predecessors according to CFG: BB#126
>>>>> %vreg373<def> = CMPLWI %vreg60, 2; CRRC:%vreg373 GPRC:%vreg60
>>>>> BCC 76, %vreg373<kill>, <BB#107>; CRRC:%vreg373
>>>>> B <BB#127>
>>>>> Successors according to CFG: BB#107(0x3ffffc00 / 0x80000000 = 50.00%) BB#127(0x40000400 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#127: derived from LLVM BB %land.lhs.true11.i.i316
>>>>> Predecessors according to CFG: BB#105
>>>>> %vreg374<def> = CMPLWI %vreg60, 0; CRRC:%vreg374 GPRC:%vreg60
>>>>> BCC 68, %vreg374<kill>, <BB#110>; CRRC:%vreg374
>>>>> B <BB#108>
>>>>> Successors according to CFG: BB#110(0x00001000 / 0x80000000 = 0.00%) BB#108(0x7ffff000 / 0x80000000 = 100.00%)
>>>>>
>>>>> BB#106: derived from LLVM BB %if.end16.i.i318
>>>>> Predecessors according to CFG: BB#104 BB#103
>>>>> %vreg377<def> = CMPLWI %vreg60, 2; CRRC:%vreg377 GPRC:%vreg60
>>>>> BCC 68, %vreg377<kill>, <BB#111>; CRRC:%vreg377
>>>>> B <BB#107>
>>>>> Successors according to CFG: BB#107(0x40000000 / 0x80000000 = 50.00%) BB#111(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#107: derived from LLVM BB %land.lhs.true20.i.i323
>>>>> Predecessors according to CFG: BB#105 BB#106
>>>>> %vreg378<def> = LD 0, <fi#7>; mem:LD8[%twine.i.i319398](tbaa=!4) G8RC_and_G8RC_NOX0:%vreg378
>>>>> %vreg379<def> = LHZ 16, %vreg378<kill>; mem:LD2[%157](align=8) GPRC:%vreg379 G8RC_and_G8RC_NOX0:%vreg378
>>>>> %vreg380<def> = RLWINM %vreg379, 0, 24, 31; GPRC:%vreg380,%vreg379
>>>>> %vreg381<def> = CMPLWI %vreg379, 256; CRRC:%vreg381 GPRC:%vreg379
>>>>> %vreg382<def> = CMPWI %vreg380<kill>, 1; CRRC:%vreg382 GPRC:%vreg380
>>>>> %vreg383<def> = COPY %vreg381:sub_lt; CRBITRC:%vreg383 CRRC:%vreg381
>>>>> %vreg384<def> = COPY %vreg382:sub_eq; CRBITRC:%vreg384 CRRC:%vreg382
>>>>> %vreg385<def> = CROR %vreg383<kill>, %vreg384<kill>; CRBITRC:%vreg385,%vreg383,%vreg384
>>>>> BC %vreg385<kill>, <BB#110>; CRBITRC:%vreg385
>>>>> B <BB#108>
>>>>> Successors according to CFG: BB#108(0x7ffff800 / 0x80000000 = 100.00%) BB#110(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#108: derived from LLVM BB %if.end23.i.i325
>>>>> Predecessors according to CFG: BB#127 BB#107
>>>>> %vreg386<def> = RLWINM %vreg59, 0, 24, 31; GPRC:%vreg386,%vreg59
>>>>> %vreg387<def> = CMPLWI %vreg386<kill>, 2; CRRC:%vreg387 GPRC:%vreg386
>>>>> BCC 68, %vreg387<kill>, <BB#111>; CRRC:%vreg387
>>>>> B <BB#109>
>>>>> Successors according to CFG: BB#109(0x40000000 / 0x80000000 = 50.00%) BB#111(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#109: derived from LLVM BB %land.lhs.true27.i.i330
>>>>> Predecessors according to CFG: BB#108
>>>>> %vreg388<def> = LD 8, <fi#7>; mem:LD8[%twine28.i.i326](tbaa=!4) G8RC_and_G8RC_NOX0:%vreg388
>>>>> %vreg389<def> = LHZ 16, %vreg388<kill>; mem:LD2[%163](align=8) GPRC:%vreg389 G8RC_and_G8RC_NOX0:%vreg388
>>>>> %vreg390<def> = RLWINM %vreg389, 0, 24, 31; GPRC:%vreg390,%vreg389
>>>>> %vreg391<def> = CMPLWI %vreg389, 255; CRRC:%vreg391 GPRC:%vreg389
>>>>> %vreg392<def> = CMPWI %vreg390<kill>, 1; CRRC:%vreg392 GPRC:%vreg390
>>>>> %vreg393<def> = COPY %vreg391:sub_gt; CRBITRC:%vreg393 CRRC:%vreg391
>>>>> %vreg394<def> = COPY %vreg392:sub_eq; CRBITRC:%vreg394 CRRC:%vreg392
>>>>> %vreg395<def> = CRANDC %vreg393<kill>, %vreg394<kill>; CRBITRC:%vreg395,%vreg393,%vreg394
>>>>> BC %vreg395<kill>, <BB#111>; CRBITRC:%vreg395
>>>>> B <BB#110>
>>>>> Successors according to CFG: BB#111(0x7ffff800 / 0x80000000 = 100.00%) BB#110(0x00000800 / 0x80000000 = 0.00%)
>>>>>
>>>>> BB#110: derived from LLVM BB %cond.false.i331
>>>>> Predecessors according to CFG: BB#126 BB#127 BB#103 BB#107 BB#109
>>>>> %vreg396<def> = ADDIStocHA %X2, <ga:@.str.36>; G8RC_and_G8RC_NOX0:%vreg396
>>>>> %vreg397<def> = LI8 274; G8RC:%vreg397
>>>>> %vreg398<def> = ADDIStocHA %X2, <ga:@.str.37>; G8RC_and_G8RC_NOX0:%vreg398
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg399<def> = ADDIStocHA %X2, <ga:@__PRETTY_FUNCTION__._ZN4llvm5TwineC2EPKc>; G8RC_and_G8RC_NOX0:%vreg399
>>>>> %vreg400<def> = ADDItocL %vreg396<kill>, <ga:@.str.36>; G8RC:%vreg400 G8RC_and_G8RC_NOX0:%vreg396
>>>>> %vreg401<def> = ADDItocL %vreg398<kill>, <ga:@.str.37>; G8RC:%vreg401 G8RC_and_G8RC_NOX0:%vreg398
>>>>> %vreg402<def> = ADDItocL %vreg399<kill>, <ga:@__PRETTY_FUNCTION__._ZN4llvm5TwineC2EPKc>; G8RC:%vreg402 G8RC_and_G8RC_NOX0:%vreg399
>>>>> %X3<def> = COPY %vreg400; G8RC:%vreg400
>>>>> %X4<def> = COPY %vreg401; G8RC:%vreg401
>>>>> %X5<def> = COPY %vreg397; G8RC:%vreg397
>>>>> %X6<def> = COPY %vreg402; G8RC:%vreg402
>>>>> BL8_NOP <ga:@__assert_fail>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>>
>>>>> BB#111: derived from LLVM BB %_ZN4llvm5TwineC2EPKc.exit333
>>>>> Predecessors according to CFG: BB#106 BB#108 BB#109
>>>>> %vreg403<def> = ADDI8 <fi#7>, 0; G8RC:%vreg403
>>>>> %vreg404<def> = LI8 0; G8RC:%vreg404
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg66; G8RC:%vreg66
>>>>> %X4<def> = COPY %vreg25; G8RC_and_G8RC_NOX0:%vreg25
>>>>> %X5<def> = COPY %vreg52; G8RC:%vreg52
>>>>> %X6<def> = COPY %vreg403; G8RC:%vreg403
>>>>> %X7<def> = COPY %vreg404; G8RC:%vreg404
>>>>> BL8_NOP <ga:@_ZN4llvm9IRBuilderILb1ENS_12TargetFolderENS_21InstCombineIRInserterEE10CreateAShrEPNS_5ValueES5_RKNS_5TwineEb>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X4<imp-use>, %X5<imp-use>, %X6<imp-use>, %X7<imp-use>, %X2<imp-use>, %R1<imp-def>, %X3<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %vreg405<def> = COPY %X3; G8RC:%vreg405
>>>>> %vreg61<def> = COPY %vreg405; G8RC:%vreg61,%vreg405
>>>>> Successors according to CFG: BB#112(?%)
>>>>>
>>>>> BB#112: derived from LLVM BB %cleanup74
>>>>> Predecessors according to CFG: BB#52 BB#50 BB#111 BB#101 BB#90 BB#63
>>>>> %vreg62<def> = PHI %vreg25, <BB#52>, %vreg25, <BB#50>, %vreg61, <BB#111>, %vreg58, <BB#101>, %vreg55, <BB#90>, %vreg45, <BB#63>; G8RC:%vreg62,%vreg61,%vreg58,%vreg55,%vreg45 G8RC_and_G8RC_NOX0:%vreg25
>>>>> %vreg483<def> = LWZ 0, <fi#0>; mem:LD4[%167](align=8)(tbaa=!15) GPRC:%vreg483
>>>>> %vreg484<def> = CMPLWI %vreg483<kill>, 65; CRRC:%vreg484 GPRC:%vreg483
>>>>> BCC 12, %vreg484<kill>, <BB#115>; CRRC:%vreg484
>>>>> B <BB#113>
>>>>> Successors according to CFG: BB#113(0x40000000 / 0x80000000 = 50.00%) BB#115(0x40000000 / 0x80000000 = 50.00%)
>>>>>
>>>>> BB#113: derived from LLVM BB %if.then.i338
>>>>> Predecessors according to CFG: BB#112
>>>>> %vreg63<def> = LD 8, <fi#0>; mem:LD8[%pVal.i336](tbaa=!4) G8RC:%vreg63
>>>>> %vreg485<def> = CMPLDI %vreg63, 0; CRRC:%vreg485 G8RC:%vreg63
>>>>> BCC 76, %vreg485<kill>, <BB#115>; CRRC:%vreg485
>>>>> B <BB#114>
>>>>> Successors according to CFG: BB#115(0x30000000 / 0x80000000 = 37.50%) BB#114(0x50000000 / 0x80000000 = 62.50%)
>>>>>
>>>>> BB#114: derived from LLVM BB %delete.notnull.i339
>>>>> Predecessors according to CFG: BB#113
>>>>> ADJCALLSTACKDOWN 112, %R1<imp-def,dead>, %R1<imp-use>
>>>>> %X3<def> = COPY %vreg63; G8RC:%vreg63
>>>>> BL8_NOP <ga:@_ZdaPv>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17 %R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21 %V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24 %VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20 %X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ %CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>, %LR8<imp-def,dead>, %RM<imp-use>, %X3<imp-use>, %X2<imp-use>, %R1<imp-def>
>>>>> ADJCALLSTACKUP 112, 0, %R1<imp-def,dead>, %R1<imp-use>
>>>>> Successors according to CFG: BB#115(?%)
>>>>>
>>>>> BB#115: derived from LLVM BB %_ZN4llvm5APIntD2Ev.exit341
>>>>> Predecessors according to CFG: BB#112 BB#113 BB#114
>>>>> Successors according to CFG: BB#116(?%)
>>>>>
>>>>> BB#116: derived from LLVM BB %cleanup85
>>>>> Predecessors according to CFG: BB#117 BB#115 BB#137
>>>>> %vreg64<def> = PHI %vreg68, <BB#117>, %vreg68, <BB#123>, %vreg130, <BB#137>, %vreg62, <BB#115>; G8RC:%vreg64,%vreg62 G8RC_and_G8RC_NOX0:%vreg68,%vreg130
>>>>> %X3<def> = COPY %vreg64; G8RC:%vreg64
>>>>> BLR8 %LR8<imp-use>, %RM<imp-use>, %X3<imp-use>
>>>>>
>>>>> # End machine code for function _ZL19simplifyX86immShiftRKN4llvm13IntrinsicInstERNS_9IRBuilderILb1ENS_12TargetFolderENS_21InstCombineIRInserterEEE.
>>>>>
>>>>> *** Bad machine code: PHI operand is not in the CFG ***
>>>>> - function: _ZL19simplifyX86immShiftRKN4llvm13IntrinsicInstERNS_9IRBuilderILb1ENS_12TargetFolderENS_21InstCombineIRInserterEEE
>>>>> - basic block: BB#116 cleanup85 (0x10009352f30)
>>>>> - instruction: %vreg64<def> = PHI
>>>>> - operand 4: <BB#123>
>>>>> fatal error: error in backend: Found 1 machine code errors.
>>>>> clang-3.8: error: clang frontend command failed with exit code 70 (use -v to see invocation)
>>>>> clang version 3.9.0 (trunk 260806)
>>>>> Target: powerpc64-unknown-linux-gnu
>>>>> Thread model: posix
>>>>> InstalledDir: /home/seurer/llvm/install/llvm-test/bin
>>>>> clang-3.8: note: diagnostic msg: PLEASE submit a bug report to http://llvm.org/bugs/ and include the crash backtrace, preprocessed source, and associated run script.
>>>>> clang-3.8: note: diagnostic msg:
>>>>> ********************
>>>>>
>>>>> PLEASE ATTACH THE FOLLOWING FILES TO THE BUG REPORT:
>>>>> Preprocessed source(s) and associated run script(s) are located at:
>>>>> clang-3.8: note: diagnostic msg: /tmp/InstCombineCalls-8e8a31.cpp
>>>>> clang-3.8: note: diagnostic msg: /tmp/InstCombineCalls-8e8a31.sh
>>>>> clang-3.8: note: diagnostic msg:
>>>>>
>>>>>
>>>>> On 02/12/16 22:35, Matthias Braun via llvm-commits wrote:
>>>>>> Author: matze
>>>>>> Date: Fri Feb 12 22:35:31 2016
>>>>>> New Revision: 260806
>>>>>>
>>>>>> URL: http://llvm.org/viewvc/llvm-project?rev=260806&view=rev
>>>>>> Log:
>>>>>> LiveIntervalAnalysis: Remove LiveVariables requirement
>>>>>>
>>>>>> This requirement was a huge hack to keep LiveVariables alive because it
>>>>>> was optionally used by TwoAddressInstructionPass and PHIElimination.
>>>>>> However we have AnalysisUsage::addUsedIfAvailable() which we can use in
>>>>>> those passes.
>>>>>>
>>>>>> Modified:
>>>>>> llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
>>>>>> llvm/trunk/lib/CodeGen/PHIElimination.cpp
>>>>>> llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
>>>>>>
>>>>>> Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=260806&r1=260805&r2=260806&view=diff
>>>>>> ==============================================================================
>>>>>> --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
>>>>>> +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Fri Feb 12 22:35:31 2016
>>>>>> @@ -9,8 +9,7 @@
>>>>>> //
>>>>>> // This file implements the LiveInterval analysis pass which is used
>>>>>> // by the Linear Scan Register allocator. This pass linearizes the
>>>>>> -// basic blocks of the function in DFS order and uses the
>>>>>> -// LiveVariables pass to conservatively compute live intervals for
>>>>>> +// basic blocks of the function in DFS order and computes live intervals for
>>>>>> // each virtual and physical register.
>>>>>> //
>>>>>> //===----------------------------------------------------------------------===//
>>>>>> @@ -48,7 +47,6 @@ char &llvm::LiveIntervalsID = LiveInterv
>>>>>> INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
>>>>>> "Live Interval Analysis", false, false)
>>>>>> INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
>>>>>> -INITIALIZE_PASS_DEPENDENCY(LiveVariables)
>>>>>> INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
>>>>>> INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
>>>>>> INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
>>>>>> @@ -77,10 +75,6 @@ void LiveIntervals::getAnalysisUsage(Ana
>>>>>> AU.setPreservesCFG();
>>>>>> AU.addRequired<AAResultsWrapperPass>();
>>>>>> AU.addPreserved<AAResultsWrapperPass>();
>>>>>> - // LiveVariables isn't really required by this analysis, it is only required
>>>>>> - // here to make sure it is live during TwoAddressInstructionPass and
>>>>>> - // PHIElimination. This is temporary.
>>>>>> - AU.addRequired<LiveVariables>();
>>>>>> AU.addPreserved<LiveVariables>();
>>>>>> AU.addPreservedID(MachineLoopInfoID);
>>>>>> AU.addRequiredTransitiveID(MachineDominatorsID);
>>>>>>
>>>>>> Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp
>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=260806&r1=260805&r2=260806&view=diff
>>>>>> ==============================================================================
>>>>>> --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original)
>>>>>> +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Fri Feb 12 22:35:31 2016
>>>>>> @@ -121,6 +121,7 @@ INITIALIZE_PASS_END(PHIElimination, "phi
>>>>>> "Eliminate PHI nodes for register allocation", false, false)
>>>>>>
>>>>>> void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
>>>>>> + AU.addUsedIfAvailable<LiveVariables>();
>>>>>> AU.addPreserved<LiveVariables>();
>>>>>> AU.addPreserved<SlotIndexes>();
>>>>>> AU.addPreserved<LiveIntervals>();
>>>>>>
>>>>>> Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=260806&r1=260805&r2=260806&view=diff
>>>>>> ==============================================================================
>>>>>> --- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
>>>>>> +++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Fri Feb 12 22:35:31 2016
>>>>>> @@ -157,6 +157,7 @@ public:
>>>>>> void getAnalysisUsage(AnalysisUsage &AU) const override {
>>>>>> AU.setPreservesCFG();
>>>>>> AU.addRequired<AAResultsWrapperPass>();
>>>>>> + AU.addUsedIfAvailable<LiveVariables>();
>>>>>> AU.addPreserved<LiveVariables>();
>>>>>> AU.addPreserved<SlotIndexes>();
>>>>>> AU.addPreserved<LiveIntervals>();
>>>>>>
>>>>>>
>>>>>> _______________________________________________
>>>>>> llvm-commits mailing list
>>>>>> llvm-commits at lists.llvm.org
>>>>>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>>>>>>
>>>>>
>>>>>
>>>>> --
>>>>>
>>>>> -Bill Seurer
>>>>>
>>>>
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at lists.llvm.org
>>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>>
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