[PATCH] D19584: AMDGPU/SI: Assembler: Unify parsing/printing of operands.

[Nikolay Haustov via llvm-commits]

nhaustov created this revision.
nhaustov added reviewers: tstellarAMD, SamWot, artem.tamazov.
nhaustov added a subscriber: llvm-commits.
Herald added subscribers: arsenm, qcolombet.

The goal is for each operand type to have its own parse function and
at the same time share common code for tracking state as different
instruction types share operand types (e.g. glc/glc_flat, etc).

Introduce parseAMDGPUOperand which can parse any optional operand.
DPP and Clamp/OMod have custom handling for now. Sam also suggested
to have class hierarchy for operand types instead of table. This
can be done in separate change.

Remove parseVOP3OptionalOps, parseDS*OptionalOps, parseFlatOptionalOps,
parseMubufOptionalOps, parseDPPOptionalOps.
Reduce number of definitions of AsmOperand's and MatchClasses' by using common base class.
Rename AsmMatcher/InstPrinter methods accordingly.
Print immediate type when printing parsed immediate operand.
Use 'off' if offset/index register is unused instead of skipping it to make it more readable (also agreed with SP3).
Update tests.

http://reviews.llvm.org/D19584

Files:
  lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
  lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h
  lib/Target/AMDGPU/SIInstrInfo.td
  test/CodeGen/AMDGPU/captured-frame-index.ll
  test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll
  test/CodeGen/AMDGPU/cgp-addressing-modes.ll
  test/CodeGen/AMDGPU/ctpop.ll
  test/CodeGen/AMDGPU/fdiv.f64.ll
  test/CodeGen/AMDGPU/fmax3.f64.ll
  test/CodeGen/AMDGPU/global_atomics.ll
  test/CodeGen/AMDGPU/global_atomics_i64.ll
  test/CodeGen/AMDGPU/half.ll
  test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll
  test/CodeGen/AMDGPU/llvm.SI.load.dword.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll
  test/CodeGen/AMDGPU/merge-stores.ll
  test/CodeGen/AMDGPU/mubuf.ll
  test/CodeGen/AMDGPU/reduce-load-width-alignment.ll
  test/CodeGen/AMDGPU/schedule-global-loads.ll
  test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
  test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
  test/CodeGen/AMDGPU/v_mac.ll
  test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
  test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
  test/MC/AMDGPU/ds-err.s
  test/MC/AMDGPU/mubuf.s
  test/MC/AMDGPU/reg-syntax-extra.s
  test/MC/Disassembler/AMDGPU/mubuf_vi.txt

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