[llvm] r267522 - [AArch64] Expand v1i64 and v2i64 ctlz.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Tue Apr 26 00:26:51 2016
New Revision: 267522

URL: http://llvm.org/viewvc/llvm-project?rev=267522&view=rev
Log:
[AArch64] Expand v1i64 and v2i64 ctlz.

The default is legal, which results in 'Cannot select' errors.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/trunk/test/CodeGen/AArch64/arm64-vclz.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=267522&r1=267521&r2=267522&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Apr 26 00:26:51 2016
@@ -595,6 +595,9 @@ AArch64TargetLowering::AArch64TargetLowe
     setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom);
     setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
 
+    setOperationAction(ISD::CTLZ,       MVT::v1i64, Expand);
+    setOperationAction(ISD::CTLZ,       MVT::v2i64, Expand);
+
     // AArch64 doesn't have MUL.2d:
     setOperationAction(ISD::MUL, MVT::v2i64, Expand);
     // Custom handling for some quad-vector types to detect MULL.

Modified: llvm/trunk/test/CodeGen/AArch64/arm64-vclz.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-vclz.ll?rev=267522&r1=267521&r2=267522&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-vclz.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-vclz.ll Tue Apr 26 00:26:51 2016
@@ -48,6 +48,18 @@ define <2 x i32> @test_vclz_s32(<2 x i32
   ret <2 x i32> %vclz1.i
 }
 
+define <1 x i64> @test_vclz_u64(<1 x i64> %a) nounwind readnone ssp {
+  ; CHECK-LABEL: test_vclz_u64:
+  %vclz1.i = tail call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %a, i1 false) nounwind
+  ret <1 x i64> %vclz1.i
+}
+
+define <1 x i64> @test_vclz_s64(<1 x i64> %a) nounwind readnone ssp {
+  ; CHECK-LABEL: test_vclz_s64:
+  %vclz1.i = tail call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %a, i1 false) nounwind
+  ret <1 x i64> %vclz1.i
+}
+
 define <16 x i8> @test_vclzq_u8(<16 x i8> %a) nounwind readnone ssp {
   ; CHECK-LABEL: test_vclzq_u8:
   ; CHECK: clz.16b v0, v0
@@ -96,12 +108,28 @@ define <4 x i32> @test_vclzq_s32(<4 x i3
   ret <4 x i32> %vclz1.i
 }
 
+define <2 x i64> @test_vclzq_u64(<2 x i64> %a) nounwind readnone ssp {
+  ; CHECK-LABEL: test_vclzq_u64:
+  %vclz1.i = tail call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 false) nounwind
+  ret <2 x i64> %vclz1.i
+}
+
+define <2 x i64> @test_vclzq_s64(<2 x i64> %a) nounwind readnone ssp {
+  ; CHECK-LABEL: test_vclzq_s64:
+  %vclz1.i = tail call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 false) nounwind
+  ret <2 x i64> %vclz1.i
+}
+
+declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone
+
 declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
 
 declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone
 
 declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) nounwind readnone
 
+declare <1 x i64> @llvm.ctlz.v1i64(<1 x i64>, i1) nounwind readnone
+
 declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone
 
 declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) nounwind readnone