[llvm] r267502 - Remove MinLatency in SchedMachineModel. NFC.
Junmo Park via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 25 17:37:46 PDT 2016
Author: flyingforyou
Date: Mon Apr 25 19:37:46 2016
New Revision: 267502
URL: http://llvm.org/viewvc/llvm-project?rev=267502&view=rev
Log:
Remove MinLatency in SchedMachineModel. NFC.
Summary:
We don't use MinLatency any more since r184032.
Reviewers: atrick, hfinkel, mcrosier
Differential Revision: http://reviews.llvm.org/D19474
Modified:
llvm/trunk/include/llvm/Target/TargetSchedule.td
llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td
llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td
llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
llvm/trunk/lib/Target/Lanai/LanaiSchedule.td
llvm/trunk/lib/Target/PowerPC/PPCSchedule440.td
llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td
llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td
llvm/trunk/lib/Target/PowerPC/PPCScheduleE5500.td
llvm/trunk/lib/Target/PowerPC/PPCScheduleG5.td
llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td
llvm/trunk/lib/Target/PowerPC/PPCScheduleP8.td
Modified: llvm/trunk/include/llvm/Target/TargetSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSchedule.td?rev=267502&r1=267501&r2=267502&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSchedule.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSchedule.td Mon Apr 25 19:37:46 2016
@@ -76,8 +76,6 @@ def instregex;
// See MCSchedule.h for detailed comments.
class SchedMachineModel {
int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle.
- int MinLatency = -1; // Determines which instructions are allowed in a group.
- // (-1) inorder (0) ooo, (1): inorder +var latencies.
int MicroOpBufferSize = -1; // Max micro-ops that can be buffered.
int LoopMicroOpBufferSize = -1; // Max micro-ops that can be buffered for
// optimized loop dispatch/execution.
Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td?rev=267502&r1=267501&r2=267502&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td Mon Apr 25 19:37:46 2016
@@ -19,7 +19,6 @@
def CortexA53Model : SchedMachineModel {
let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order.
let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
- let MinLatency = 1 ; // OperandCycles are interpreted as MinLatency.
let LoadLatency = 3; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td?rev=267502&r1=267501&r2=267502&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td Mon Apr 25 19:37:46 2016
@@ -19,7 +19,6 @@
def ExynosM1Model : SchedMachineModel {
let IssueWidth = 4; // Up to 4 uops per cycle.
- let MinLatency = 0; // OoO.
let MicroOpBufferSize = 96; // ROB size.
let LoopMicroOpBufferSize = 32; // Instruction queue size.
let LoadLatency = 4; // Optimistic load cases.
Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA8.td?rev=267502&r1=267501&r2=267502&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA8.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA8.td Mon Apr 25 19:37:46 2016
@@ -1065,7 +1065,6 @@ def CortexA8Itineraries : ProcessorItine
// Cortex-A8 machine model for scheduling and other instruction cost heuristics.
def CortexA8Model : SchedMachineModel {
let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
- let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
let LoadLatency = 2; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
Modified: llvm/trunk/lib/Target/Lanai/LanaiSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiSchedule.td?rev=267502&r1=267501&r2=267502&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiSchedule.td (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiSchedule.td Mon Apr 25 19:37:46 2016
@@ -39,10 +39,6 @@ def LanaiSchedModel : SchedMachineModel
// Max micro-ops that may be scheduled per cycle. [default = 1]
let IssueWidth = 1;
- // Determines which instructions are allowed in a group. 1 is an inorder
- // CPU with variable latencies. [default = -1]
- let MinLatency = 1;
-
// Extra cycles for a mispredicted branch. [default = -1]
let MispredictPenalty = 10;
Modified: llvm/trunk/lib/Target/PowerPC/PPCSchedule440.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSchedule440.td?rev=267502&r1=267501&r2=267502&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSchedule440.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSchedule440.td Mon Apr 25 19:37:46 2016
@@ -597,7 +597,6 @@ def PPC440Itineraries : ProcessorItinera
def PPC440Model : SchedMachineModel {
let IssueWidth = 2; // 2 instructions are dispatched per cycle.
- let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
let LoadLatency = 5; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td?rev=267502&r1=267501&r2=267502&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td Mon Apr 25 19:37:46 2016
@@ -160,7 +160,6 @@ def PPCA2Itineraries : ProcessorItinerar
def PPCA2Model : SchedMachineModel {
let IssueWidth = 1; // 1 instruction is dispatched per cycle.
- let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
let LoadLatency = 6; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td?rev=267502&r1=267501&r2=267502&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td Mon Apr 25 19:37:46 2016
@@ -311,7 +311,6 @@ def PPCE500mcItineraries : ProcessorItin
def PPCE500mcModel : SchedMachineModel {
let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
- let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
let LoadLatency = 5; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleE5500.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleE5500.td?rev=267502&r1=267501&r2=267502&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleE5500.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleE5500.td Mon Apr 25 19:37:46 2016
@@ -371,7 +371,6 @@ def PPCE5500Itineraries : ProcessorItine
def PPCE5500Model : SchedMachineModel {
let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
- let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
let LoadLatency = 6; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleG5.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleG5.td?rev=267502&r1=267501&r2=267502&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleG5.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleG5.td Mon Apr 25 19:37:46 2016
@@ -118,7 +118,6 @@ def G5Itineraries : ProcessorItineraries
def G5Model : SchedMachineModel {
let IssueWidth = 4; // 4 (non-branch) instructions are dispatched per cycle.
- let MinLatency = 0; // Out-of-order dispatch.
let LoadLatency = 3; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td?rev=267502&r1=267501&r2=267502&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td Mon Apr 25 19:37:46 2016
@@ -382,7 +382,6 @@ def P7Model : SchedMachineModel {
// branches), but the total internal issue bandwidth per
// cycle (from all queues) is 8.
- let MinLatency = 0; // Out-of-order dispatch.
let LoadLatency = 3; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleP8.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleP8.td?rev=267502&r1=267501&r2=267502&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleP8.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleP8.td Mon Apr 25 19:37:46 2016
@@ -391,7 +391,6 @@ def P8Model : SchedMachineModel {
// up to six non-branch instructions.
// up to two branches in a dispatch group.
- let MinLatency = 0; // Out-of-order dispatch.
let LoadLatency = 3; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
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