[PATCH] D18645: [mips][microMIPS] Fix offsets for LLE, LWE, SBE, SCE and SHE instructions

Simon Dardis via llvm-commits llvm-commits at lists.llvm.org
Mon Apr 25 05:40:50 PDT 2016

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sdardis accepted this revision.
sdardis added a reviewer: sdardis.
sdardis added a comment.

LGTM. There is another occurrence of taking 12 bit offsets that should be 9 which is the cache and pref instructions definitions for microMIPS32r6.


http://reviews.llvm.org/D18645

Previous message: [PATCH] D19466: [Clang][Builtin][AVX512]Adding k-register logic intrinsics KAND, KANDN, KOR, KORTEST, KXNOR, KXOR, KUNPACK instruction set.
Next message: [PATCH] D18645: [mips][microMIPS] Fix offsets for LLE, LWE, SBE, SCE and SHE instructions
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