[PATCH] D19202: [PR27390] [CodeGen] Reject indexed loads in CombinerDAG.

[Hal Finkel via llvm-commits]

hfinkel added inline comments.

================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:3102
@@ -3097,3 +3101,3 @@
        N0.getValueSizeInBits() == N0.getOperand(0).getScalarValueSizeInBits() &&
-       N0.getOperand(0).getOpcode() == ISD::LOAD) ||
-      N0.getOpcode() == ISD::LOAD) {
+       ISD::isUNINDEXEDLoad(N0.getOperand(0).getNode()))||
+      ISD::isUNINDEXEDLoad(N0.getNode())) {
----------------
It is not clear this is necessary; the code below explicitly handles indexed loads:

      if (Load->getExtensionType() == ISD::EXTLOAD) {
        NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
                              Load->getValueType(0), SDLoc(Load),
                              Load->getChain(), Load->getBasePtr(),
                              Load->getOffset(), Load->getMemoryVT(),
                              Load->getMemOperand());
        // Replace uses of the EXTLOAD with the new ZEXTLOAD.
        if (Load->getNumValues() == 3) {
          // PRE/POST_INC loads have 3 values.
          SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
                           NewLoad.getValue(2) };
          CombineTo(Load, To, 3, true);

================
Comment at: lib/CodeGen/SelectionDAG/SelectionDAG.cpp:6965
@@ -6964,1 +6964,3 @@
     return false;
+  if (LD->isIndexed() || Base->isIndexed())
+    return false;
----------------
Why?


Repository:
  rL LLVM

http://reviews.llvm.org/D19202