[PATCH] D19449: Add optimization bisect opt-in calls for AArch64 passes
Andy Kaylor via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 22 17:36:00 PDT 2016
andrew.w.kaylor created this revision.
andrew.w.kaylor added a reviewer: t.p.northover.
andrew.w.kaylor added a subscriber: llvm-commits.
andrew.w.kaylor set the repository for this revision to rL LLVM.
Herald added subscribers: rengolin, aemerson.
This patch adds calls to ARM-specific passes that can be safely skipped to opt-in to the optimization bisect mechanism.
I am not adding opt-in calls to the following passes, which appear to be required:
ARMConstantIslands
ARMExpandPseudo
Thumb2ITBlockPass
Note that the call to skipFunction() will also check for the "optnone" function attribute, so this can theoretically result in passes being skipped even when optimization bisect is not being done. However, I believe that any pass that can be safely skipped should be skipped for functions with the optnone attribute.
Repository:
rL LLVM
http://reviews.llvm.org/D19449
Files:
lib/Target/ARM/A15SDOptimizer.cpp
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
lib/Target/ARM/ARMOptimizeBarriersPass.cpp
lib/Target/ARM/MLxExpansionPass.cpp
lib/Target/ARM/Thumb2SizeReduction.cpp
Index: lib/Target/ARM/A15SDOptimizer.cpp
===================================================================
--- lib/Target/ARM/A15SDOptimizer.cpp
+++ lib/Target/ARM/A15SDOptimizer.cpp
@@ -681,6 +681,9 @@
}
bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) {
+ if (skipFunction(*Fn.getFunction()))
+ return false;
+
const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>();
// Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
// enabled when NEON is available.
Index: lib/Target/ARM/ARMLoadStoreOptimizer.cpp
===================================================================
--- lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -1887,6 +1887,9 @@
}
bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
+ if (skipFunction(*Fn.getFunction()))
+ return false;
+
MF = &Fn;
STI = &static_cast<const ARMSubtarget &>(Fn.getSubtarget());
TL = STI->getTargetLowering();
@@ -1962,7 +1965,7 @@
ARM_PREALLOC_LOAD_STORE_OPT_NAME, false, false)
bool ARMPreAllocLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
- if (AssumeMisalignedLoadStores)
+ if (AssumeMisalignedLoadStores || skipFunction(*Fn.getFunction()))
return false;
TD = &Fn.getDataLayout();
Index: lib/Target/ARM/ARMOptimizeBarriersPass.cpp
===================================================================
--- lib/Target/ARM/ARMOptimizeBarriersPass.cpp
+++ lib/Target/ARM/ARMOptimizeBarriersPass.cpp
@@ -51,6 +51,9 @@
}
bool ARMOptimizeBarriersPass::runOnMachineFunction(MachineFunction &MF) {
+ if (skipFunction(*MF.getFunction()))
+ return false;
+
// Vector to store the DMBs we will remove after the first iteration
std::vector<MachineInstr *> ToRemove;
// DMBType is the Imm value of the first operand. It determines whether it's a
Index: lib/Target/ARM/MLxExpansionPass.cpp
===================================================================
--- lib/Target/ARM/MLxExpansionPass.cpp
+++ lib/Target/ARM/MLxExpansionPass.cpp
@@ -378,6 +378,9 @@
}
bool MLxExpansion::runOnMachineFunction(MachineFunction &Fn) {
+ if (skipFunction(*Fn.getFunction()))
+ return false;
+
TII = static_cast<const ARMBaseInstrInfo *>(Fn.getSubtarget().getInstrInfo());
TRI = Fn.getSubtarget().getRegisterInfo();
MRI = &Fn.getRegInfo();
Index: lib/Target/ARM/Thumb2SizeReduction.cpp
===================================================================
--- lib/Target/ARM/Thumb2SizeReduction.cpp
+++ lib/Target/ARM/Thumb2SizeReduction.cpp
@@ -1025,7 +1025,8 @@
}
bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) {
- if (PredicateFtor && !PredicateFtor(*MF.getFunction()))
+ if (skipFunction(*MF.getFunction()) ||
+ PredicateFtor && !PredicateFtor(*MF.getFunction()))
return false;
STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
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