[PATCH] D19349: MachineScheduler: Limit the size of the ready list.
Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 22 12:15:12 PDT 2016
This revision was automatically updated to reflect the committed changes.
Closed by commit rL267189: MachineScheduler: Limit the size of the ready list. (authored by matze).
Changed prior to commit:
http://reviews.llvm.org/D19349?vs=54603&id=54700#toc
Repository:
rL LLVM
http://reviews.llvm.org/D19349
Files:
llvm/trunk/lib/CodeGen/MachineScheduler.cpp
llvm/trunk/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
Index: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp
+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp
@@ -64,6 +64,11 @@
static bool ViewMISchedDAGs = false;
#endif // NDEBUG
+/// Avoid quadratic complexity in unusually large basic blocks by limiting the
+/// size of the ready lists.
+static cl::opt<unsigned> ReadyListLimit("misched-limit", cl::Hidden,
+ cl::desc("Limit ready list to N instructions"), cl::init(256));
+
static cl::opt<bool> EnableRegPressure("misched-regpressure", cl::Hidden,
cl::desc("Enable register pressure scheduling."), cl::init(true));
@@ -1956,7 +1961,8 @@
// Check for interlocks first. For the purpose of other heuristics, an
// instruction that cannot issue appears as if it's not in the ReadyQueue.
bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
- if ((!IsBuffered && ReadyCycle > CurrCycle) || checkHazard(SU))
+ if ((!IsBuffered && ReadyCycle > CurrCycle) || checkHazard(SU) ||
+ Available.size() >= ReadyListLimit)
Pending.push(SU);
else
Available.push(SU);
@@ -2211,6 +2217,9 @@
if (checkHazard(SU))
continue;
+ if (Available.size() >= ReadyListLimit)
+ break;
+
Available.push(SU);
Pending.remove(Pending.begin()+i);
--i; --e;
Index: llvm/trunk/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
+++ llvm/trunk/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
@@ -1,5 +1,6 @@
; REQUIRES: asserts
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - -misched-limit=2 2>&1 > /dev/null | FileCheck %s
;
; The Cortex-A53 machine model will cause the MADD instruction to be scheduled
; much higher than the ADD instructions in order to hide latency. When not
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