[PATCH] D16917: [mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructions

[Simon Dardis via llvm-commits]

sdardis requested changes to this revision.
sdardis added a comment.
This revision now requires changes to proceed.

Can you rebase and repost this patch?

You should also extend test/CodeGen/Mips/countleading.ll and test/CodeGen/Mips/mips64shift.ll for checking microMIPS64R6 for these instructions.


================
Comment at: lib/Target/Mips/MicroMips64r6InstrFormats.td:118
@@ +117,3 @@
+
+class POOL32S_2RSA5_FM_MMR6<string instr_asm, bits<9> funct> {
+  bits<5> rt;
----------------
Rename this to POOL32S_2R_SA5_FM_MMR6. Putting a '_' between the 2R and SA5 makes it a bit clearer that this class describes a instruction with a 2 register and shift amount of 5 form.

================
Comment at: lib/Target/Mips/Mips64InstrInfo.td:260-261
@@ -257,4 +259,4 @@
 /// Count Leading
 def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
 def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
 
----------------
These need to be marked NoInMicroMips too.

================
Comment at: test/MC/Mips/micromips64r6/valid.s:157
@@ -154,1 +156,3 @@
+        drotr32 $1, $2, 4        # CHECK: drotr32 $1, $2, 4       # encoding: [0x58,0x22,0x20,0xc8]
+        drotrv $3, $6, $4        # CHECK: drotrv $3, $6, $4       # encoding: [0x58,0xc4,0x18,0xd0]
 1:
----------------
Please restore the blank line at the end.


http://reviews.llvm.org/D16917