[PATCH] D18366: Factor PrologEpilogInserter around spilling, frame finalization, and scavenging

[Quentin Colombet via llvm-commits]

qcolombet added inline comments.

================
Comment at: lib/CodeGen/PrologEpilogInserter.cpp:69
@@ +68,3 @@
+    // XXX replace this with some sort of target hook
+    if (TM && (TM->getTargetTriple().getArch() == Triple::wasm32 ||
+               TM->getTargetTriple().getArch() == Triple::wasm64)) {
----------------
dschuff wrote:
> For the target hook you could almost use `TargetRegisterInfo::getCalleeSavedRegs()` (if CSRs is empty, then you can skip spilling) but that requires a MachineFunction because it depends on the calling convention. We could add something like `TargetRegisterInfo::usesCalleeSavedRegs()` or even come full circle to something like in D15394 :)
I don’t like the name in D15394, in particular the mention of register allocation (it is antinomic to me to have both virtual register and after regalloc in the same name :)).
The problem with usesCalleeSavedRegs is that it does not convey the information that we want or do not want to scavenge the virtual registers used for frame. 

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Comment at: lib/CodeGen/PrologEpilogInserter.cpp:87
@@ +86,3 @@
+    if (UsesCalleeSaves)
+      MFP.set(MachineFunctionProperties::Property::AllVRegsAllocated);
+    return MFP;
----------------
I do not like that UsesCalleeSaves implies all vregs are allocated. That is the same naming problem I mentioned previously, We need to come up with a name for the hook that conveys all that information at once. usesPhysReg for PEI?


http://reviews.llvm.org/D18366