[PATCH] D19378: [mips] Fix select patterns for MIPS64

[Simon Dardis via llvm-commits]

sdardis created this revision.
sdardis added reviewers: dsanders, vkalintiris.
sdardis added subscribers: petarj, llvm-commits.
sdardis set the repository for this revision to rL LLVM.
Herald added subscribers: sdardis, dsanders.

When targetting MIPS64R6 some of the patterns for select were guarded by a
broken predicate. The predicate was supposed to test if a constant value
could fit in a 16 bit zero-extended field. Instead the value was tested to
fit in a 16 bit sign-extended field. For negative constants of native word
width this resulted in wrong code generation.

Repository:
  rL LLVM

http://reviews.llvm.org/D19378

Files:
  lib/Target/Mips/Mips64InstrInfo.td
  test/CodeGen/Mips/llvm-ir/select-int.ll

Index: test/CodeGen/Mips/llvm-ir/select-int.ll
===================================================================
--- test/CodeGen/Mips/llvm-ir/select-int.ll
+++ test/CodeGen/Mips/llvm-ir/select-int.ll
@@ -160,3 +160,43 @@
   %r = select i1 %s, i64 %x, i64 %y
   ret i64 %r
 }
+
+define i8* @tst_select_word_cst(i8* %a, i8* %b) {
+  ; ALL-LABEL: tst_select_i64_cst:
+
+  ; M2:         addiu   $1, $zero, -1
+  ; M2:         xor     $1, $5, $1
+  ; M2:         sltu    $1, $zero, $1
+  ; M2:         bnez    $1, $[[BB0:BB[0-9_]+]]
+  ; M2:         addiu   $2, $zero, 0
+  ; M2:         move    $2, $4
+  ; M2: $[[BB0]]:
+  ; M2:         jr      $ra
+
+  ; CMOV-32:    addiu   $1, $zero, -1
+  ; CMOV-32:    xor     $1, $5, $1
+  ; CMOV-32:    movn    $4, $zero, $1
+  ; CMOV-32:    jr      $ra
+  ; CMOV-32:    move    $2, $4
+
+  ; SEL-32:     addiu   $1, $zero, -1
+  ; SEL-32:     xor     $1, $5, $1
+  ; SEL-32:     sltu    $1, $zero, $1
+  ; SEL-32:     jr      $ra
+  ; SEL-32:     seleqz  $2, $4, $1
+
+  ; CMOV-64:    daddiu  $1, $zero, -1
+  ; CMOV-64:    xor     $1, $5, $1
+  ; CMOV-64:    movn    $4, $zero, $1
+  ; CMOV-64:    move    $2, $4
+
+  ; SEL-64:     daddiu  $1, $zero, -1
+  ; SEL-64:     xor     $1, $5, $1
+  ; SEL-64:     sltu    $1, $zero, $1
+  ; SEL-64:	sll     $1, $1, 0
+  ; SEL-64:	seleqz  $2, $4, $1
+
+  %cmp = icmp eq i8* %b, inttoptr (i64 -1 to i8*)
+  %r = select i1 %cmp, i8* %a, i8* null
+  ret i8* %r
+}
Index: lib/Target/Mips/Mips64InstrInfo.td
===================================================================
--- lib/Target/Mips/Mips64InstrInfo.td
+++ lib/Target/Mips/Mips64InstrInfo.td
@@ -29,7 +29,7 @@
                            [{ return isInt<10>(N->getSExtValue()); }]>;
 
 def immZExt16_64 : PatLeaf<(i64 imm),
-                           [{ return isInt<16>(N->getZExtValue()); }]>;
+                           [{ return isUInt<16>(N->getZExtValue()); }]>;
 
 def immZExt5_64 : ImmLeaf<i64, [{ return Imm == (Imm & 0x1f); }]>;
 


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