[PATCH] D17913: AVX512BW: Support llvm intrinsic masked vector load/store for i8/i16 element types on SKX

[Ayal Zaks via llvm-commits]

Ayal added a subscriber: Ayal.

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Comment at: llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp:1442
@@ -1442,1 +1441,3 @@
+  return (DataWidth >= 32 && ST->hasAVX()) ||
+         (DataWidth >= 8 && ST->hasBWI());
 }
----------------
Following comment in Analysis/TargetTransformInfo.h should be augmented to indicate targets that also allow this for 8 and 16 bit elements:

  /// \brief Return true if the target supports masked gather/scatter
  /// AVX2 and AVX-512 targets allow masks for consecutive load and store for
  /// 32 and 64 bit elements.
  bool isLegalMaskedStore(Type *DataType) const;
  bool isLegalMaskedLoad(Type *DataType) const;



Repository:
  rL LLVM

http://reviews.llvm.org/D17913