[PATCH] D15744: [mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions

[Simon Dardis via llvm-commits]

sdardis added a subscriber: sdardis.
sdardis added a reviewer: sdardis.
sdardis added a comment.

Can you rebase and repost?

Thanks.


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Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:259
@@ -259,1 +258,3 @@
+class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, II_MUL, mulhs>;
 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
+class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUL, mulhu>;
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Is there any reason why this one is not changed?

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Comment at: lib/Target/Mips/Mips32r6InstrInfo.td:723-732
@@ -722,10 +722,12 @@
 def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6;
 let AdditionalPredicates = [NotInMicroMips] in {
   def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
 }
-def MUH    : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6;
-def MUHU   : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
-def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
-def MULU   : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6;
+let AdditionalPredicates = [NotInMicroMips] in {
+  def MUH    : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6;
+  def MUHU   : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
+  def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
+  def MULU   : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6;
+}
 def NAL; // BAL with rd=0
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These two blocks can be joined together but leave a blank line between the fp msubfs and the integer multiplies.

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Comment at: lib/Target/Mips/Mips64InstrInfo.td:385
@@ -386,1 +384,3 @@
+  def DMUL  : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
+              ADD_FM<0x1c, 0x03>, ISA_NOT_MICROMIPS_NOT_64R6;
 
----------------
This is the Octeon multiply, you're looking to change DMULT I believe.

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Comment at: test/MC/Mips/micromips64r6/valid.s:153-160
@@ -152,2 +152,10 @@
         di $15                   # CHECK: di $15                  # encoding: [0x00,0x0f,0x47,0x7c]
+        mul $3, $4, $5           # CHECK mul $3, $4, $5       # encoding: [0x00,0xa4,0x18,0x18]
+        muh $3, $4, $5           # CHECK muh $3, $4, $5       # encoding: [0x00,0xa4,0x18,0x58]
+        mulu $3, $4, $5          # CHECK mulu $3, $4, $5      # encoding: [0x00,0xa4,0x18,0x98]
+        muhu $3, $4, $5          # CHECK muhu $3, $4, $5      # encoding: [0x00,0xa4,0x18,0xd8]
+        dmul $3, $4, $5          # CHECK dmul $3, $4, $5      # encoding: [0x58,0xa4,0x18,0x18]
+        dmuh $3, $4, $5          # CHECK dmuh $3, $4, $5      # encoding: [0x58,0xa4,0x18,0x58]
+        dmulu $3, $4, $5         # CHECK dmulu $3, $4, $5     # encoding: [0x58,0xa4,0x18,0x98]
+        dmuhu $3, $4, $5         # CHECK dmuhu $3, $4, $5     # encoding: [0x58,0xa4,0x18,0xd8]
 
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Line up the "# encoding.." parts with the rest of the file.


http://reviews.llvm.org/D15744