[llvm] r266977 - [mips][microMIPS] Implement LL, SC, MOVEP, ROTR, ROTRV and SYSCALL instructions and add tests for LWM32 and SWM32
Zlatko Buljan via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 21 04:01:52 PDT 2016
Author: zbuljan
Date: Thu Apr 21 06:01:51 2016
New Revision: 266977
URL: http://llvm.org/viewvc/llvm-project?rev=266977&view=rev
Log:
[mips][microMIPS] Implement LL, SC, MOVEP, ROTR, ROTRV and SYSCALL instructions and add tests for LWM32 and SWM32
Differential Revision: http://reviews.llvm.org/D19150
Modified:
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt
llvm/trunk/test/MC/Mips/micromips/invalid-wrong-error.s
llvm/trunk/test/MC/Mips/micromips/invalid.s
llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s
llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
llvm/trunk/test/MC/Mips/micromips32r6/valid.s
llvm/trunk/test/MC/Mips/micromips64r6/invalid-wrong-error.s
llvm/trunk/test/MC/Mips/micromips64r6/invalid.s
llvm/trunk/test/MC/Mips/micromips64r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=266977&r1=266976&r2=266977&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Thu Apr 21 06:01:51 2016
@@ -1144,7 +1144,15 @@ public:
(R0 == Mips::A0 && R1 == Mips::S6) ||
(R0 == Mips::A0 && R1 == Mips::A1) ||
(R0 == Mips::A0 && R1 == Mips::A2) ||
- (R0 == Mips::A0 && R1 == Mips::A3))
+ (R0 == Mips::A0 && R1 == Mips::A3) ||
+ (R0 == Mips::A1_64 && R1 == Mips::A2_64) ||
+ (R0 == Mips::A1_64 && R1 == Mips::A3_64) ||
+ (R0 == Mips::A2_64 && R1 == Mips::A3_64) ||
+ (R0 == Mips::A0_64 && R1 == Mips::S5_64) ||
+ (R0 == Mips::A0_64 && R1 == Mips::S6_64) ||
+ (R0 == Mips::A0_64 && R1 == Mips::A1_64) ||
+ (R0 == Mips::A0_64 && R1 == Mips::A2_64) ||
+ (R0 == Mips::A0_64 && R1 == Mips::A3_64))
return true;
return false;
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=266977&r1=266976&r2=266977&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Thu Apr 21 06:01:51 2016
@@ -1031,4 +1031,7 @@ def : MipsInstAlias<"tltu $rs, $rt",
(TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tne $rs, $rt",
(TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+def : MipsInstAlias<"rotr $rt, $imm",
+ (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;
+def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>;
}
Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td?rev=266977&r1=266976&r2=266977&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td Thu Apr 21 06:01:51 2016
@@ -758,8 +758,8 @@ def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC,
def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
+ def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6;
}
-def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6;
def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;
def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
@@ -793,10 +793,8 @@ def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_
let AdditionalPredicates = [NotInMicroMips] in {
def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
-}
-def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
-let AdditionalPredicates = [NotInMicroMips] in {
-def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
+ def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
+ def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
}
def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=266977&r1=266976&r2=266977&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Apr 21 06:01:51 2016
@@ -1705,11 +1705,13 @@ def SRAV : MMRel, shift_rotate_reg<"srav
SRLV_FM<7, 0>;
// Rotate Instructions
-def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
- immZExt5>,
- SRA_FM<2, 1>, ISA_MIPS32R2;
-def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
- SRLV_FM<6, 1>, ISA_MIPS32R2;
+let AdditionalPredicates = [NotInMicroMips] in {
+ def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
+ immZExt5>,
+ SRA_FM<2, 1>, ISA_MIPS32R2;
+ def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
+ SRLV_FM<6, 1>, ISA_MIPS32R2;
+}
/// Load and Store Instructions
/// aligned
@@ -2223,7 +2225,9 @@ def : MipsInstAlias<"beqz $rs,$offset",
(BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
def : MipsInstAlias<"beqzl $rs,$offset",
(BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
-def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
+let AdditionalPredicates = [NotInMicroMips] in {
+ def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
+}
def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt?rev=266977&r1=266976&r2=266977&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt Thu Apr 21 06:01:51 2016
@@ -189,3 +189,5 @@
0x04 0x63 0x02 0x64 # CHECK: lwle $24, 2($4)
0x44 0x60 0x08 0x6c # CHECK: lle $2, 8($4)
0x44 0x60 0x08 0xac # CHECK: sce $2, 8($4)
+0x00 0x00 0x7c 0x8b # CHECK: syscall
+0x8c 0x01 0x7c 0x8b # CHECK: syscall 396
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt?rev=266977&r1=266976&r2=266977&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt Thu Apr 21 06:01:51 2016
@@ -189,3 +189,5 @@
0x63 0x04 0x64 0x02 # CHECK: lwle $24, 2($4)
0x60 0x44 0x6c 0x08 # CHECK: lle $2, 8($4)
0x60 0x44 0xac 0x08 # CHECK: sce $2, 8($4)
+0x00 0x00 0x8b 0x7c # CHECK: syscall
+0x01 0x8c 0x8b 0x7c # CHECK: syscall 396
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt?rev=266977&r1=266976&r2=266977&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt Thu Apr 21 06:01:51 2016
@@ -21,6 +21,7 @@
0x29 0x82 # CHECK: lhu16 $3, 4($16)
0x09 0x94 # CHECK: lbu16 $3, 4($17)
0x09 0x9f # CHECK: lbu16 $3, -1($17)
+0x84 0x34 # CHECK: movep $5, $6, $2, $3
0x04 0xcc # CHECK: addu16 $6, $17, $4
0x44 0x21 # CHECK: and16 $16, $2
0x2e 0x56 # CHECK: andi16 $4, $5, 8
@@ -73,6 +74,15 @@
0x00 0x01 0xf3 0x7c # CHECK: eretnc
0x80 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256
+0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4)
+0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4)
+0x21 0x3b 0x59 0x84 # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27)
+0x01 0x26 0x38 0xc0 # CHECK: rotr $9, $6, 7
+0x00 0xc7 0x48 0xd0 # CHECK: rotrv $9, $6, $7
+0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4)
+0x20 0x44 0xd0 0x08 # CHECK: swm32 $16, $17, 8($4)
+0x00 0x00 0x8b 0x7c # CHECK: syscall
+0x01 0x8c 0x8b 0x7c # CHECK: syscall 396
0xbd 0x0a 0x01 0x2c # CHECK: ldc1 $f8, 300($10)
0x21 0x6c 0x23 0xff # CHECK: ldc2 $11, 1023($12)
0x78 0x48 0x00 0x43 # CHECK: lwpc $2, 268
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt?rev=266977&r1=266976&r2=266977&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt Thu Apr 21 06:01:51 2016
@@ -21,6 +21,16 @@
0x45 0x2b # CHECK: jalr $9
0x45 0x23 # CHECK: jrc16 $9
0x44 0xb3 # CHECK: jrcaddiusp 20
+0x84 0x34 # CHECK: movep $5, $6, $2, $3
+0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4)
+0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4)
+0x21 0x3b 0x59 0x84 # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27)
+0x01 0x26 0x38 0xc0 # CHECK: rotr $9, $6, 7
+0x00 0xc7 0x48 0xd0 # CHECK: rotrv $9, $6, $7
+0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4)
+0x20 0x44 0xd0 0x08 # CHECK: swm32 $16, $17, 8($4)
+0x00 0x00 0x8b 0x7c # CHECK: syscall
+0x01 0x8c 0x8b 0x7c # CHECK: syscall 396
0xf0 0x64 0x00 0x05 # CHECK: daui $3, $4, 5
0x42 0x23 0x00 0x04 # CHECK: dahi $3, 4
0x42 0x03 0x00 0x04 # CHECK: dati $3, 4
Modified: llvm/trunk/test/MC/Mips/micromips/invalid-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips/invalid-wrong-error.s?rev=266977&r1=266976&r2=266977&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips/invalid-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/micromips/invalid-wrong-error.s Thu Apr 21 06:01:51 2016
@@ -9,4 +9,5 @@
sdbbp -1 # CHECK: :[[@LINE]]:9: error: expected 20-bit unsigned immediate
sdbbp 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
+ syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/micromips/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips/invalid.s?rev=266977&r1=266976&r2=266977&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips/invalid.s Thu Apr 21 06:01:51 2016
@@ -39,7 +39,11 @@
pref 32, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
prefe 0, -513($7) # CHECK: :[[@LINE]]:12: error: expected memory with 9-bit signed offset
prefe 0, 512($7) # CHECK: :[[@LINE]]:12: error: expected memory with 9-bit signed offset
+ rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
+ rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
+ rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
+ rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
sdbbp16 -1 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
sdbbp16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
sll $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
Modified: llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s?rev=266977&r1=266976&r2=266977&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s Thu Apr 21 06:01:51 2016
@@ -27,3 +27,6 @@
tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
+ syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
+ syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/invalid.s?rev=266977&r1=266976&r2=266977&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/invalid.s Thu Apr 21 06:01:51 2016
@@ -121,3 +121,19 @@
mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mfhc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mfhc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
+ lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
+ lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
+ lwm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
+ lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $24, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
+ movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ movep $5, $21, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
+ rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
+ rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
+ rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
+ rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
+ swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
+ swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=266977&r1=266976&r2=266977&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Thu Apr 21 06:01:51 2016
@@ -71,6 +71,28 @@
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43]
lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
+ ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08]
+ lwm32 $16, $17, 8($4) # CHECK: lwm32 $16, $17, 8($4) # encoding: [0x20,0x44,0x50,0x08]
+ lwm32 $16, $17, 8($sp) # CHECK: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08]
+ lwm32 $16, $17, $ra, 8($4) # CHECK: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08]
+ lwm32 $16, $17, $ra, 64($sp) # CHECK: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0x50,0x40]
+ lwm32 $16, $17, $18, $19, 8($4) # CHECK: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08]
+ lwm32 $16, $17, $18, $19, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $ra, 8($4) # encoding: [0x22,0x84,0x50,0x08]
+ lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # encoding: [0x21,0x24,0x50,0x08]
+ lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
+ lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
+ movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34]
+ rotr $2, 7 # CHECK: rotr $2, $2, 7 # encoding: [0x00,0x42,0x38,0xc0]
+ rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
+ rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
+ sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08]
+ swm32 $16, $17, 8($4) # CHECK: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08]
+ swm32 $16, $17, 8($sp) # CHECK: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08]
+ swm32 $16, $17, $ra, 8($4) # CHECK: swm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0xd0,0x08]
+ swm32 $16, $17, $ra, 64($sp) # CHECK: swm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0xd0,0x40]
+ swm32 $16, $17, $18, $19, 8($4) # CHECK: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08]
+ syscall # CHECK: syscall # encoding: [0x00,0x00,0x8b,0x7c]
+ syscall 396 # CHECK: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c]
mod $3, $4, $5 # CHECK: mod $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x58]
modu $3, $4, $5 # CHECK: modu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd8]
mul $3, $4, $5 # CHECK mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18]
Modified: llvm/trunk/test/MC/Mips/micromips64r6/invalid-wrong-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/invalid-wrong-error.s?rev=266977&r1=266976&r2=266977&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/invalid-wrong-error.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/invalid-wrong-error.s Thu Apr 21 06:01:51 2016
@@ -27,3 +27,6 @@
tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
dins $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
dins $2, $3, 32, 1 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
+ syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
+ syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/micromips64r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/invalid.s?rev=266977&r1=266976&r2=266977&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/invalid.s Thu Apr 21 06:01:51 2016
@@ -146,3 +146,19 @@
dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
+ lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
+ lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
+ lwm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
+ lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $24, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
+ movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ movep $5, $21, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
+ rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
+ rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
+ rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
+ rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
+ swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
+ swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
Modified: llvm/trunk/test/MC/Mips/micromips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/valid.s?rev=266977&r1=266976&r2=266977&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/valid.s Thu Apr 21 06:01:51 2016
@@ -27,6 +27,28 @@ a:
lhu16 $3, 4($16) # CHECK: lhu16 $3, 4($16) # encoding: [0x29,0x82]
lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94]
lbu16 $3, -1($17) # CHECK: lbu16 $3, -1($17) # encoding: [0x09,0x9f]
+ movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34]
+ ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08]
+ lwm32 $16, $17, 8($4) # CHECK: lwm32 $16, $17, 8($4) # encoding: [0x20,0x44,0x50,0x08]
+ lwm32 $16, $17, 8($sp) # CHECK: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08]
+ lwm32 $16, $17, $ra, 8($4) # CHECK: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08]
+ lwm32 $16, $17, $ra, 64($sp) # CHECK: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0x50,0x40]
+ lwm32 $16, $17, $18, $19, 8($4) # CHECK: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08]
+ lwm32 $16, $17, $18, $19, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $ra, 8($4) # encoding: [0x22,0x84,0x50,0x08]
+ lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # encoding: [0x21,0x24,0x50,0x08]
+ lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
+ lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
+ rotr $2, 7 # CHECK: rotr $2, $2, 7 # encoding: [0x00,0x42,0x38,0xc0]
+ rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
+ rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
+ sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08]
+ swm32 $16, $17, 8($4) # CHECK: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08]
+ swm32 $16, $17, 8($sp) # CHECK: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08]
+ swm32 $16, $17, $ra, 8($4) # CHECK: swm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0xd0,0x08]
+ swm32 $16, $17, $ra, 64($sp) # CHECK: swm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0xd0,0x40]
+ swm32 $16, $17, $18, $19, 8($4) # CHECK: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08]
+ syscall # CHECK: syscall # encoding: [0x00,0x00,0x8b,0x7c]
+ syscall 396 # CHECK: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c]
ddiv $3, $4, $5 # CHECK: ddiv $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x18]
dmod $3, $4, $5 # CHECK: dmod $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x58]
ddivu $3, $4, $5 # CHECK: ddivu $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x98]
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