[PATCH] D19354: [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructions

[Simon Dardis via llvm-commits]

sdardis accepted this revision.
sdardis added a comment.
This revision is now accepted and ready to land.

LGTM with those 2 nits addressed.


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Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:984-986
@@ -983,3 +983,5 @@
 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
-      MMR6Arch<"addu16">;
+      MMR6Arch<"addu16"> {
+  int AddedComplexity  = 1;
+}
 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
----------------
This change should be separate. Also, what's the reason behind this change?

================
Comment at: lib/Target/Mips/MipsInstrInfo.td:1651-1661
@@ -1650,11 +1650,13 @@
             ISA_MIPS1_NOT_32R6_64R6;
+let AdditionalPredicates = [NotInMicroMips] in {
 def SLTi  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
             SLTI_FM<0xa>;
 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
             SLTI_FM<0xb>;
+}
 let AdditionalPredicates = [NotInMicroMips] in {
 def ANDi  : MMRel, StdMMR6Rel,
             ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>,
             ADDI_FM<0xc>;
 }
 def ORi   : MMRel, StdMMR6Rel,
----------------
Join these blocks together.


http://reviews.llvm.org/D19354