[PATCH] D16719: [mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and NOR instructions
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 21 02:18:21 PDT 2016
sdardis added a subscriber: sdardis.
sdardis added a reviewer: sdardis.
================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:1226
@@ +1225,3 @@
+def : MipsInstAlias<"and $rs, $rt, $imm",
+ (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>,
+ ISA_MICROMIPS32R6;
----------------
Shouldn't the immediate by of type uimm16 ?
================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:1229
@@ +1228,3 @@
+def : MipsInstAlias<"and $rs, $imm",
+ (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>,
+ ISA_MICROMIPS32R6;
----------------
Here too.
================
Comment at: lib/Target/Mips/MicroMipsInstrInfo.td:1006
@@ -1002,3 +1005,3 @@
(LW_MM addr:$addr)>;
//===----------------------------------------------------------------------===//
----------------
Can you provide a terminating } for the let Predicates = [InMicroMips] (line 966 of the diff} here.
================
Comment at: lib/Target/Mips/MicroMipsInstrInfo.td:1010
@@ -1006,3 +1009,3 @@
//===----------------------------------------------------------------------===//
class UncondBranchMMPseudo<string opstr> :
----------------
Move the "let Predicates = [InMicroMips] in {" from line 1022 to line 1010. Then you can remove the closing branch on line 1020 and have this aliases section guarded clearly.
================
Comment at: lib/Target/Mips/MipsInstrInfo.td:1368-1384
@@ -1367,19 +1367,19 @@
def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
let AdditionalPredicates = [NotInMicroMips] in {
def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
ADD_FM<0, 0x24>;
def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
ADD_FM<0, 0x25>;
def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
ADD_FM<0, 0x26>;
-}
def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
+}
/// Shift Instructions
let AdditionalPredicates = [NotInMicroMips] in {
def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
immZExt5>, SRA_FM<0, 0>;
def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
immZExt5>, SRA_FM<2, 0>;
}
def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
----------------
These two "let AdditionalPredicates =" blocks can be joined together.
================
Comment at: test/CodeGen/Mips/llvm-ir/and.ll:45
@@ -33,1 +44,3 @@
+
+ ; MM64: nop
----------------
Near ToT is not giving me this nop and the other nops. I see it with certain broken combinations of options (e.g. mips64 and +micromips).
================
Comment at: test/CodeGen/Mips/llvm-ir/and.ll:155-252
@@ -102,1 +154,99 @@
}
+
+define signext i1 @and_i1_4(i1 signext %b) {
+entry:
+; ALL-LABEL: and_i1_4:
+
+ ; GP32: addiu $2, $zero, 0
+
+ ; GP64: addiu $2, $zero, 0
+
+ ; MMR6: lui $2, 0
+
+ %r = and i1 4, %b
+ ret i1 %r
+}
+
+define signext i8 @and_i8_4(i8 signext %b) {
+entry:
+; ALL-LABEL: and_i8_4:
+
+ ; GP32: andi $2, $4, 4
+
+ ; GP64: andi $2, $4, 4
+
+ ; MMR6: andi16 $2, $4, 4
+
+ %r = and i8 4, %b
+ ret i8 %r
+}
+
+define signext i16 @and_i16_4(i16 signext %b) {
+entry:
+; ALL-LABEL: and_i16_4:
+
+ ; GP32: andi $2, $4, 4
+
+ ; GP64: andi $2, $4, 4
+
+ ; MMR6: andi16 $2, $4, 4
+
+ %r = and i16 4, %b
+ ret i16 %r
+}
+
+define signext i32 @and_i32_4(i32 signext %b) {
+entry:
+; ALL-LABEL: and_i32_4:
+
+ ; GP32: andi $2, $4, 4
+
+ ; GP64: andi $2, $4, 4
+
+ ; MMR6: andi16 $2, $4, 4
+
+ %r = and i32 4, %b
+ ret i32 %r
+}
+
+define signext i64 @and_i64_4(i64 signext %b) {
+entry:
+; ALL-LABEL: and_i64_4:
+
+ ; GP32: andi $3, $5, 4
+ ; GP32: addiu $2, $zero, 0
+
+ ; GP64: andi $2, $4, 4
+
+ ; MM32: andi16 $3, $5, 4
+ ; MM32: lui $2, 0
+
+ ; MM64: andi $2, $4, 4
+
+ %r = and i64 4, %b
+ ret i64 %r
+}
+
+define signext i128 @and_i128_4(i128 signext %b) {
+entry:
+; ALL-LABEL: and_i128_4:
+
+ ; GP32: andi $5, $7, 4
+ ; GP32: addiu $2, $zero, 0
+ ; GP32: addiu $3, $zero, 0
+ ; GP32: addiu $4, $zero, 0
+
+ ; GP64: andi $3, $5, 4
+ ; GP64: daddiu $2, $zero, 0
+
+ ; MM32: andi16 $5, $7, 4
+ ; MM32: lui $2, 0
+ ; MM32: lui $3, 0
+ ; MM32: lui $4, 0
+
+ ; MM64: andi $3, $5, 4
+ ; MM64: daddiu $2, $zero, 0
+
+ %r = and i128 4, %b
+ ret i128 %r
+}
----------------
Check some other constants other than 4 that are encodable. Also add 1 or 2 cases where the value is not encodable in 16bit form and check that a normal andi is generated.
================
Comment at: test/CodeGen/Mips/llvm-ir/or.ll:266
@@ +265,2 @@
+ ret i128 %r
+}
----------------
As with the andi case, check some other short form encodable constants and add 1or 2 cases where the constant is not encodable in the 16bit form for andi.
================
Comment at: test/MC/Mips/micromips32r6/valid.s:253
@@ -252,1 +252,3 @@
deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c]
+ and $3, $4, 5 # CHECK: andi $3, $4, 5 # encoding: [0xd0,0x64,0x00,0x05]
+ and $3, 5 # CHECK: andi $3, $3, 5 # encoding: [0xd0,0x63,0x00,0x05]
----------------
Indentation for the "#encoding..."
================
Comment at: test/MC/Mips/micromips64r6/valid.s:153-169
@@ -152,2 +152,19 @@
di $15 # CHECK: di $15 # encoding: [0x00,0x0f,0x47,0x7c]
+ and16 $16, $2 # CHECK: and16 $16, $2 # encoding: [0x44,0x21]
+ andi16 $4, $5, 8 # CHECK: andi16 $4, $5, 8 # encoding: [0x2e,0x56]
+ and $3, $4, $5 # CHECK: and $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x50]
+ andi $3, $4, 1234 # CHECK: andi $3, $4, 1234 # encoding: [0xd0,0x64,0x04,0xd2]
+ or16 $3, $7 # CHECK: or16 $3, $7 # encoding: [0x45,0xf9]
+ or $3, $4, $5 # CHECK: or $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x90]
+ ori $3, $4, 1234 # CHECK: ori $3, $4, 1234 # encoding: [0x50,0x64,0x04,0xd2]
+ xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10]
+ xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2]
+ and $3, $4, 5 # CHECK: andi $3, $4, 5 # encoding: [0xd0,0x64,0x00,0x05]
+ and $3, 5 # CHECK: andi $3, $3, 5 # encoding: [0xd0,0x63,0x00,0x05]
+ or $3, $4, 5 # CHECK: ori $3, $4, 5 # encoding: [0x50,0x64,0x00,0x05]
+ or $3, 5 # CHECK: ori $3, $3, 5 # encoding: [0x50,0x63,0x00,0x05]
+ xor $3, $4, 5 # CHECK: xori $3, $4, 5 # encoding: [0x70,0x64,0x00,0x05]
+ xor $3, 5 # CHECK: xori $3, $3, 5 # encoding: [0x70,0x63,0x00,0x05]
+ nor $3, $4, $5 # CHECK: nor $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xd0]
+ not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x04,0x1a,0xd0]
----------------
Indentation for the "#encoding..."
http://reviews.llvm.org/D16719
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