[PATCH] D18352: [mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructions

[Simon Dardis via llvm-commits]

sdardis added inline comments.

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Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:943
@@ -938,1 +942,3 @@
 
+class BRANCH_COP1_MMR6_DESC_BASE<string opstr> : BRANCH_DESC_BASE, HARDFLOAT {
+  dag InOperandList = (ins FGR64Opnd:$ft, brtarget_mm:$offset);
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sdardis wrote:
> Formatting, break the line after "BRANCH_DESC_BASE," and indent "HARDFLOAT {" appropriately.
class BRANCH_COP1_MMR6_DESC also needs to inherit the relevant parameterised InstSE<> class.

This instruction should also define the register $at, like all other branches. $at is required to be defined by these instructions in case a long branch fixup needs to be emitted. 

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Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:952
@@ +951,3 @@
+
+class BRANCH_COP2_MMR6_DESC_BASE<string opstr> : BRANCH_DESC_BASE {
+  dag InOperandList = (ins COP2Opnd:$ct, brtarget_mm:$offset);
----------------
This instruction needs to define at as well, but you can skip the InstSE<> class inheritance as COP2 is implementation specific and likely to be targeted by intrinsics anyway.


http://reviews.llvm.org/D18352