[llvm] r266821 - [Hexagon] Fix operand swapping in HexagonPeephole

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Tue Apr 19 16:36:24 2016
New Revision: 266821

URL: http://llvm.org/viewvc/llvm-project?rev=266821&view=rev
Log:
[Hexagon] Fix operand swapping in HexagonPeephole

Also, disable zero- and size-extend optimizations for now.

Added:
    llvm/trunk/test/CodeGen/Hexagon/peephole-op-swap.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp?rev=266821&r1=266820&r2=266821&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp Tue Apr 19 16:36:24 2016
@@ -67,11 +67,11 @@ static cl::opt<bool> DisablePNotP("disab
     cl::desc("Disable Optimization of PNotP"));
 
 static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext",
-    cl::Hidden, cl::ZeroOrMore, cl::init(false),
+    cl::Hidden, cl::ZeroOrMore, cl::init(true),
     cl::desc("Disable Optimization of Sign/Zero Extends"));
 
 static cl::opt<bool> DisableOptExtTo64("disable-hexagon-opt-ext-to-64",
-    cl::Hidden, cl::ZeroOrMore, cl::init(false),
+    cl::Hidden, cl::ZeroOrMore, cl::init(true),
     cl::desc("Disable Optimization of extensions to i64."));
 
 namespace llvm {
@@ -308,6 +308,7 @@ void HexagonPeephole::ChangeOpInto(Machi
     case MachineOperand::MO_Register:
       if (Src.isReg()) {
         Dst.setReg(Src.getReg());
+        Dst.setSubReg(Src.getSubReg());
       } else if (Src.isImm()) {
         Dst.ChangeToImmediate(Src.getImm());
       } else {
@@ -322,6 +323,7 @@ void HexagonPeephole::ChangeOpInto(Machi
         Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(),
                              Src.isKill(), Src.isDead(), Src.isUndef(),
                              Src.isDebug());
+        Dst.setSubReg(Src.getSubReg());
       } else {
         llvm_unreachable("Unexpected src operand type");
       }

Added: llvm/trunk/test/CodeGen/Hexagon/peephole-op-swap.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/peephole-op-swap.ll?rev=266821&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/peephole-op-swap.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/peephole-op-swap.ll Tue Apr 19 16:36:24 2016
@@ -0,0 +1,30 @@
+; RUN: llc -march=hexagon < %s
+; REQUIRES: asserts
+
+; The operand-swapping code in HexagonPeephole was not handling subregisters
+; correctly, resulting in a crash on this code.
+
+target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
+target triple = "hexagon"
+
+ at float_rounding_mode = external global i8, align 1
+ at float_exception_flags = external global i8, align 1
+
+; Function Attrs: nounwind
+define i64 @fred(i32 %a) #0 {
+entry:
+  br i1 undef, label %cleanup, label %lor.lhs.false
+
+lor.lhs.false:                                    ; preds = %entry
+  %cmp3 = icmp eq i32 undef, 255
+  %tobool4 = icmp ne i32 undef, 0
+  %or.cond = and i1 %tobool4, %cmp3
+  %. = select i1 %or.cond, i64 9223372036854775807, i64 -9223372036854775808
+  br label %cleanup
+
+cleanup:                                          ; preds = %lor.lhs.false, %entry
+  %retval.0 = phi i64 [ 9223372036854775807, %entry ], [ %., %lor.lhs.false ]
+  ret i64 %retval.0
+}
+
+attributes #0 = { nounwind }