[llvm] r266811 - [Hexagon] Fix printing the address operand of S2_storerinewabs
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 19 13:20:34 PDT 2016
Author: kparzysz
Date: Tue Apr 19 15:20:33 2016
New Revision: 266811
URL: http://llvm.org/viewvc/llvm-project?rev=266811&view=rev
Log:
[Hexagon] Fix printing the address operand of S2_storerinewabs
Added:
llvm/trunk/test/CodeGen/Hexagon/storerinewabs.ll
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
llvm/trunk/test/CodeGen/Hexagon/absaddr-store.ll
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=266811&r1=266810&r2=266811&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Tue Apr 19 15:20:33 2016
@@ -3447,9 +3447,9 @@ multiclass ST_Abs<string mnemonic, strin
//===----------------------------------------------------------------------===//
let hasSideEffects = 0, isPredicable = 1, mayStore = 1, isNVStore = 1,
isNewValue = 1, opNewValue = 1 in
-class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp, bit isAbs>
- : NVInst_V4<(outs), (ins u32Imm:$addr, IntRegs:$src),
- mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src.new",
+class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp>
+ : NVInst_V4<(outs), (ins ImmOp:$addr, IntRegs:$src),
+ mnemonic #"(#$addr) = $src.new",
[], "", V2LDST_tc_st_SLOT0> {
bits<19> addr;
bits<3> src;
@@ -3460,7 +3460,6 @@ class T_StoreAbsGP_NV <string mnemonic,
!if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
!if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
/* u16_0Imm */ addr{15-0})));
- let Uses = !if (isAbs, [], [GP]);
let IClass = 0b0100;
let Inst{27} = 1;
@@ -3480,7 +3479,7 @@ class T_StoreAbsGP_NV <string mnemonic,
let hasSideEffects = 0, isPredicated = 1, mayStore = 1, isNVStore = 1,
isNewValue = 1, opNewValue = 2, opExtentBits = 6, opExtendable = 1 in
class T_StoreAbs_NV_Pred <string mnemonic, bits<2> MajOp, bit isNot, bit isNew>
- : NVInst_V4<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, IntRegs:$src2),
+ : NVInst_V4<(outs), (ins PredRegs:$src1, u32MustExt:$absaddr, IntRegs:$src2),
!if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
") ")#mnemonic#"(#$absaddr) = $src2.new",
[], "", ST_tc_st_SLOT0>, AddrModeRel {
@@ -3510,7 +3509,7 @@ class T_StoreAbs_NV_Pred <string mnemoni
// absolute addressing.
//===----------------------------------------------------------------------===//
class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp>
- : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 1>, AddrModeRel {
+ : T_StoreAbsGP_NV <mnemonic, u32MustExt, MajOp>, AddrModeRel {
string ImmOpStr = !cast<string>(ImmOp);
let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
@@ -3572,7 +3571,7 @@ defm storerf : ST_Abs <"memh", "STrif",
// if ([!]Pv[.new]) mem[bhwd](##global)=Rt
//===----------------------------------------------------------------------===//
-let isAsmParserOnly = 1 in
+let Uses = [GP], isAsmParserOnly = 1 in
class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC,
Operand ImmOp, bits<2> MajOp, bit isHalf = 0>
: T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, 0, isHalf> {
@@ -3582,7 +3581,7 @@ class T_StoreGP <string mnemonic, string
let BaseOpcode = BaseOp#_abs;
}
-let isAsmParserOnly = 1 in
+let Uses = [GP], isAsmParserOnly = 1 in
multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp,
bits<2> MajOp, bit isHalf = 0> {
// Set BaseOpcode same as absolute addressing instructions so that
@@ -3592,7 +3591,7 @@ multiclass ST_GP <string mnemonic, strin
def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp,
0, isHalf>;
// New-value store
- def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 0> ;
+ def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp> ;
}
}
Modified: llvm/trunk/test/CodeGen/Hexagon/absaddr-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/absaddr-store.ll?rev=266811&r1=266810&r2=266811&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/absaddr-store.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/absaddr-store.ll Tue Apr 19 15:20:33 2016
@@ -1,6 +1,5 @@
; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s
; Check that we generate load instructions with absolute addressing mode.
-; XFAIL: *
@a0 = external global i32
@a1 = external global i32
Added: llvm/trunk/test/CodeGen/Hexagon/storerinewabs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/storerinewabs.ll?rev=266811&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/storerinewabs.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/storerinewabs.ll Tue Apr 19 15:20:33 2016
@@ -0,0 +1,17 @@
+; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s
+
+ at global = external global i32, align 4
+
+; There was a bug causing ### to be printed. Make sure we print ## instead.
+; CHECK-LABEL: foo
+; CHECK: memw(##global) =
+
+define void @foo(i32 %x) #0 {
+entry:
+ %add = add nsw i32 %x, 1
+ store i32 %add, i32* @global, align 4
+ ret void
+}
+
+attributes #0 = { norecurse nounwind }
+
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