[PATCH] D18640: [mips][microMIPS]Implement CFC*, CTC* and LDC* instructions

[Simon Dardis via llvm-commits]

sdardis accepted this revision.
sdardis added a comment.
This revision is now accepted and ready to land.

LGTM with the highlighted nits addressed.


================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:680-682
@@ +679,5 @@
+
+class LDWC1_DESC_BASE<
+    string opstr, RegisterOperand RC, InstrItinClass Itin,
+    SDPatternOperator OpNode = null_frag> : MipsR6Inst, HARDFLOAT {
+  dag InOperandList = (ins mem_mm_16:$addr);
----------------
Formatting should be like: 

   class LDWC1_DESC_BASE<string opstr, RegisterOperand RC, InstrItinClass Itin,                                           
                         SDPatternOperator OpNode = null_frag> : MipsR6Inst,                                              
                         HARDFLOAT {

You can start a newline in the parameter list.

================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:698-700
@@ +697,5 @@
+
+class COP2LD_MMR6_DESC_BASE<
+    string opstr, RegisterOperand COPOpnd, InstrItinClass Itin,
+    SDPatternOperator OpNode = null_frag> {
+  dag OutOperandList = (outs COPOpnd:$rt);
----------------
The formatting should be like:

   class COP2LD_MMR6_DESC_BASE<string opstr, RegisterOperand COPOpnd,
                               InstrItinClass Itin,
                               SDPatternOperator OpNode = null_frag> {


================
Comment at: test/MC/Mips/micromips32r6/valid.s:42-45
@@ -41,2 +41,6 @@
   clz $sp, $gp             # CHECK: clz $sp, $gp        # encoding: [0x03,0x80,0xe8,0x50]
+  cfc1 $1, $2              # CHECK: cfc1 $1, $2            # encoding: [0x54,0x22,0x10,0x3b]
+  cfc2 $3, $4              # CHECK: cfc2 $3, $4            # encoding: [0x00,0x64,0xcd,0x3c]
+  ctc1 $5, $6              # CHECK: ctc1 $5, $6            # encoding: [0x54,0xa6,0x18,0x3b]
+  ctc2 $7, $8              # CHECK: ctc2 $7, $8            # encoding: [0x00,0xe8,0xdd,0x3c]
   div $3, $4, $5           # CHECK: div $3, $4, $5      # encoding: [0x00,0xa4,0x19,0x18]
----------------
Line up the "# encoding: .." with the others.

================
Comment at: test/MC/Mips/micromips32r6/valid.s:62-63
@@ -57,2 +61,4 @@
   jrcaddiusp 20            # CHECK: jrcaddiusp 20       # encoding: [0x44,0xb3]
+  ldc1 $f8, 300($10)       # CHECK: ldc1 $f8, 300($10)     # encoding: [0xbd,0x0a,0x01,0x2c]
+  ldc2 $11, 1023($12)      # CHECK: ldc2 $11, 1023($12)    # encoding: [0x21,0x6c,0x23,0xff]
   lsa $2, $3, $4, 3        # CHECK: lsa  $2, $3, $4, 3  # encoding: [0x00,0x43,0x24,0x0f]
----------------
And here.

================
Comment at: test/MC/Mips/mips32r5/invalid.s:14
@@ -15,1 +13,3 @@
+        ldc2 $11, -32769($12)   # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+        ldc2 $11, 32768($12)    # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
         mtc0  $4, $3, -1     # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
----------------
Line up this check line with the rest. The top one is ok. 

================
Comment at: test/MC/Mips/mips64r5/invalid.s:20
@@ +19,3 @@
+        ldc2 $11, -32769($12)   # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+        ldc2 $11, 32768($12)    # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset
+        pref -1, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
----------------
Same again here.

================
Comment at: test/MC/Mips/mips64r6/invalid.s:12
@@ -11,6 +11,3 @@
         align   $4, $2, $3, -1    # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate
         align   $4, $2, $3, 4     # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate
         break -1          # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
----------------
Restore the jalr.hb lines and submit that as a separate NFC change.

================
Comment at: test/MC/Mips/mips64r6/invalid.s:35-38
@@ -37,2 +34,6 @@
         dlsa    $2, $3, $4, 5     # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4
+        dmtc0  $4, $3, -1    # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
+        dmtc0  $4, $3, 8     # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
+        dmfc0  $4, $3, -1    # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
+        dmfc0  $4, $3, 8     # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
         drotr32 $2, $3, -1   # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
----------------
Submit this as a separate change.


http://reviews.llvm.org/D18640