[PATCH] D19246: Do not rename a tied operand in AggressiveAntiDepBreaker

[Brendon Cahoon via llvm-commits]

bcahoon created this revision.
bcahoon added reviewers: hfinkel, llvm-commits.

The anti-dependence breaking code should not attempt to rename an operand that is tied. Otherwise, the two operand will end up with different registers.  It appears that a similar check is made in CriticalAntiDepBreaker.

This is a failure I was seeing in the Hexagon. Unfortunately, I don't have a test case that fails with the in-tree Hexagon code.  The failure in the machine verifier with the message "Two-address instruction operands must be identical" from the following instruction.

- instruction: %R21<def,tied1> = M2_acci
- operand 1:   %R17<kill,tied0>

Prior to the anti dependence breaker (D10 is equivalent to R20 and R21).

        %D10<def> = L4_loadrd_abs <ga:@Y+24>; 
        ...
        %R21<def,tied1> = M2_acci %R21<kill,tied0>, %R2<kill>, %R20<kill>, %D10<imp-def>
 
And, then after (D8 is equivalent to R16 and R17)

         %D8<def> = L4_loadrd_abs <ga:@Y+24>
         ,,,,
         %R21<def,tied1> = M2_acci %R17<kill,tied0>, %R2<kill>, %R16<kill>, %D10<imp-def>



http://reviews.llvm.org/D19246

Files:
  lib/CodeGen/AggressiveAntiDepBreaker.cpp

Index: lib/CodeGen/AggressiveAntiDepBreaker.cpp
===================================================================
--- lib/CodeGen/AggressiveAntiDepBreaker.cpp
+++ lib/CodeGen/AggressiveAntiDepBreaker.cpp
@@ -369,7 +369,7 @@
     // reference either system calls or the register directly. Skip it until we
     // can tell user specified registers from compiler-specified.
     if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) ||
-        MI.isInlineAsm()) {
+        MI.isInlineAsm() || MI.isRegTiedToUseOperand(i)) {
       DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
       State->UnionGroups(Reg, 0);
     }
@@ -464,7 +464,7 @@
     // for the register.
     HandleLastUse(Reg, Count, "(last-use)");
 
-    if (Special) {
+    if (Special || MI.isRegTiedToDefOperand(i)) {
       DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
       State->UnionGroups(Reg, 0);
     }


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