[llvm] r266617 - [AMDGPU][llvm-mc] s_setreg* - Fix order of operands

[Artem Tamazov via llvm-commits]

Author: artem.tamazov
Date: Mon Apr 18 09:54:26 2016
New Revision: 266617

URL: http://llvm.org/viewvc/llvm-project?rev=266617&view=rev
Log:
[AMDGPU][llvm-mc] s_setreg* - Fix order of operands

Order should match the sp3 syntax, where destination (simm16 denoting the hwreg) is coming first.

Differential Revision: http://reviews.llvm.org/D19161

Modified:
    llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
    llvm/trunk/test/MC/AMDGPU/sopk.s
    llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_vi.txt

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=266617&r1=266616&r2=266617&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Mon Apr 18 09:54:26 2016
@@ -423,13 +423,13 @@ defm S_GETREG_B32 : SOPK_32 <sopk<0x12,
 
 defm S_SETREG_B32 : SOPK_m <
   sopk<0x13, 0x12>, "s_setreg_b32", (outs),
-  (ins SReg_32:$sdst, u16imm:$simm16), " $sdst, $simm16"
+  (ins SReg_32:$sdst, u16imm:$simm16), " $simm16, $sdst"
 >;
 // FIXME: Not on SI?
 //defm S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32", []>;
 defm S_SETREG_IMM32_B32 : SOPK_IMM32 <
   sopk<0x15, 0x14>, "s_setreg_imm32_b32", (outs),
-  (ins i32imm:$imm, u16imm:$simm16), " $imm, $simm16"
+  (ins i32imm:$imm, u16imm:$simm16), " $simm16, $imm"
 >;
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/test/MC/AMDGPU/sopk.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/sopk.s?rev=266617&r1=266616&r2=266617&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/sopk.s (original)
+++ llvm/trunk/test/MC/AMDGPU/sopk.s Mon Apr 18 09:54:26 2016
@@ -77,10 +77,10 @@ s_getreg_b32 s2, 0x6
 // SICI: s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb9]
 // VI:   s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb8]
 
-s_setreg_b32 s2, 0x6
-// SICI: s_setreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb9]
-// VI:   s_setreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb9]
+s_setreg_b32 0x6, s2
+// SICI: s_setreg_b32 0x6, s2 ; encoding: [0x06,0x00,0x82,0xb9]
+// VI:   s_setreg_b32 0x6, s2 ; encoding: [0x06,0x00,0x02,0xb9]
 
-s_setreg_imm32_b32 0xff, 0x6
-// SICI: s_setreg_imm32_b32 0xff, 0x6 ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00]
-// VI:   s_setreg_imm32_b32 0xff, 0x6 ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00]
+s_setreg_imm32_b32 0x6, 0xff
+// SICI: s_setreg_imm32_b32 0x6, 0xff ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00]
+// VI:   s_setreg_imm32_b32 0x6, 0xff ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00]

Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_vi.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_vi.txt?rev=266617&r1=266616&r2=266617&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_vi.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_vi.txt Mon Apr 18 09:54:26 2016
@@ -51,8 +51,8 @@
 # VI:   s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb8]
 0x06 0x00 0x82 0xb8
 
-# VI:   s_setreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb9]
+# VI:   s_setreg_b32 0x6, s2 ; encoding: [0x06,0x00,0x02,0xb9]
 0x06 0x00 0x02 0xb9
 
-# VI:   s_setreg_imm32_b32 0xff, 0x6 ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00]
+# VI:   s_setreg_imm32_b32 0x6, 0xff ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00]
 0x06 0x00 0x00 0xba 0xff 0x00 0x00 0x00