[PATCH] D19166: [mips] Prevent double-filling of delay slots by generating '.set noreorder' regions.

[Daniel Sanders via llvm-commits]

dsanders created this revision.
dsanders added reviewers: sdardis, vkalintiris.
dsanders added a subscriber: llvm-commits.
dsanders added a dependency: D19164: [mips][ias] Stream macro expansions to output instead of buffering them. NFC..
Herald added subscribers: sdardis, dsanders.

When clang is given -save-temps or -via-file-asm, any inline assembly in
the source is parsed twice. Once by the compiler, and again by the
assembler. We must take care to ensure that this doesn't lead to
double-filling delay slots.

Depends on D19164

http://reviews.llvm.org/D19166

Files:
  lib/Target/Mips/AsmParser/MipsAsmParser.cpp
  test/MC/Mips/double-expand.s

Index: test/MC/Mips/double-expand.s
===================================================================
--- /dev/null
+++ test/MC/Mips/double-expand.s
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple=mipsel-unknown-linux < %s | FileCheck %s
+# RUN: llvm-mc -triple=mipsel-unknown-linux < %s | \
+# RUN:     llvm-mc -triple=mipsel-unknown-linux | FileCheck %s
+
+# CHECK: bnez $2, foo
+# CHECK: nop
+# CHECK-NOT: nop
+
+        .text
+	bnez $2, foo
Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp
===================================================================
--- lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -1931,6 +1931,11 @@
     }
   }
 
+  bool FillDelaySlot =
+      MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder();
+  if (FillDelaySlot)
+    getTargetStreamer().emitDirectiveSetNoReorder();
+
   MacroExpanderResultTy ExpandResult =
       tryExpandInstruction(Inst, IDLoc, Out, STI);
   switch (ExpandResult) {
@@ -1945,8 +1950,10 @@
 
   // If this instruction has a delay slot and .set reorder is active,
   // emit a NOP after it.
-  if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder())
+  if (FillDelaySlot) {
     createNop(hasShortDelaySlot(Inst.getOpcode()), IDLoc, Out, STI);
+    getTargetStreamer().emitDirectiveSetReorder();
+  }
 
   if ((Inst.getOpcode() == Mips::JalOneReg ||
        Inst.getOpcode() == Mips::JalTwoReg || ExpandedJalSym) &&


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