[PATCH] D17661: [AArch64] Add MMOs to callee-save load/store instructions.

[Geoff Berry via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL266439: [AArch64] Add MMOs to callee-save load/store instructions. (authored by gberry).

Changed prior to commit:
  http://reviews.llvm.org/D17661?vs=50618&id=53893#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D17661

Files:
  llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
  llvm/trunk/test/CodeGen/AArch64/arm64-csldst-mmo.ll

Index: llvm/trunk/test/CodeGen/AArch64/arm64-csldst-mmo.ll
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-csldst-mmo.ll
+++ llvm/trunk/test/CodeGen/AArch64/arm64-csldst-mmo.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched=0 -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
+
+ at G = external global [0 x i32], align 4
+
+; Check that MMOs are added to epilogue calle-save restore loads so
+; that the store to G is not considered dependant on the callee-save
+; loads.
+;
+; CHECK: Before post-MI-sched:
+; CHECK-LABEL: # Machine code for function test1:
+; CHECK: SU(2):   STRWui %WZR
+; CHECK: SU(3):   %X21<def>, %X20<def> = LDPXi %SP
+; CHECK:  Predecessors:
+; CHECK-NEXT:   out SU(0)
+; CHECK-NEXT:   out SU(0)
+; CHECK-NEXT:   ch  SU(0)
+; CHECK-NEXT:  Successors:
+define void @test1() {
+entry:
+  tail call void asm sideeffect "nop", "~{x20},~{x21},~{x22},~{x23}"() nounwind
+  store i32 0, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @G, i64 0, i64 0), align 4
+  ret void
+}
Index: llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -871,13 +871,19 @@
         .addReg(AArch64::SP)
         .addImm(Offset) // [sp, #offset * 8], where factor * 8 is implicit
         .setMIFlag(MachineInstr::FrameSetup);
+      MIB.addMemOperand(MF.getMachineMemOperand(
+          MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx + 1),
+          MachineMemOperand::MOStore, 8, 8));
     } else {
       MBB.addLiveIn(Reg1);
       MIB.addReg(Reg1, getPrologueDeath(MF, Reg1))
         .addReg(AArch64::SP)
         .addImm(BumpSP ? Offset * 8 : Offset) // pre-inc version is unscaled
         .setMIFlag(MachineInstr::FrameSetup);
     }
+    MIB.addMemOperand(MF.getMachineMemOperand(
+        MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx),
+        MachineMemOperand::MOStore, 8, 8));
   }
   return true;
 }
@@ -935,18 +941,25 @@
     if (BumpSP)
       MIB.addReg(AArch64::SP, RegState::Define);
 
-    if (RPI.isPaired())
+    if (RPI.isPaired()) {
       MIB.addReg(Reg2, getDefRegState(true))
         .addReg(Reg1, getDefRegState(true))
         .addReg(AArch64::SP)
         .addImm(Offset) // [sp], #offset * 8  or [sp, #offset * 8]
                         // where the factor * 8 is implicit
         .setMIFlag(MachineInstr::FrameDestroy);
-    else
+      MIB.addMemOperand(MF.getMachineMemOperand(
+          MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx + 1),
+          MachineMemOperand::MOLoad, 8, 8));
+    } else {
       MIB.addReg(Reg1, getDefRegState(true))
         .addReg(AArch64::SP)
         .addImm(BumpSP ? Offset * 8 : Offset) // post-dec version is unscaled
         .setMIFlag(MachineInstr::FrameDestroy);
+    }
+    MIB.addMemOperand(MF.getMachineMemOperand(
+        MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx),
+        MachineMemOperand::MOLoad, 8, 8));
   }
   return true;
 }


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