[llvm] r266412 - [X86] AND, OR, and XOR of vectors are always legal no need to set them legal explicitly.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 14 23:20:15 PDT 2016
Author: ctopper
Date: Fri Apr 15 01:20:14 2016
New Revision: 266412
URL: http://llvm.org/viewvc/llvm-project?rev=266412&view=rev
Log:
[X86] AND, OR, and XOR of vectors are always legal no need to set them legal explicitly.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=266412&r1=266411&r2=266412&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Apr 15 01:20:14 2016
@@ -1465,11 +1465,6 @@ X86TargetLowering::X86TargetLowering(con
// Custom lower several nodes.
for (MVT VT : MVT::vector_valuetypes()) {
unsigned EltSize = VT.getVectorElementType().getSizeInBits();
- if (EltSize == 1) {
- setOperationAction(ISD::AND, VT, Legal);
- setOperationAction(ISD::OR, VT, Legal);
- setOperationAction(ISD::XOR, VT, Legal);
- }
if ((VT.is128BitVector() || VT.is256BitVector()) && EltSize >= 32) {
setOperationAction(ISD::MGATHER, VT, Custom);
setOperationAction(ISD::MSCATTER, VT, Custom);
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