[PATCH] D19132: AMDGPU: Correct reported code size

[Matt Arsenault via llvm-commits]

arsenm created this revision.
arsenm added reviewers: tstellarAMD, vpykhtin, SamWot.
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Herald added a subscriber: arsenm.

For a while this has been counting many instructions as 0,
so the printed code size comment hasn't been very meaningful.
    
This sets the instruction size to 8 for all 64-bit instructions.
For instructions which may include an additional 4 byte literal,
it is set to 0 because the size must be determined from the operands.
    
This currently breaks the disassembler for all of the 4-byte
instructions which may have a literal.

http://reviews.llvm.org/D19132

Files:
  lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
  lib/Target/AMDGPU/CIInstructions.td
  lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
  lib/Target/AMDGPU/SIInstrFormats.td
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.h
  lib/Target/AMDGPU/SIInstrInfo.td
  test/CodeGen/AMDGPU/hsa.ll

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