[PATCH] D18687: [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructions

[Simon Dardis via llvm-commits]

sdardis accepted this revision.
sdardis added a reviewer: sdardis.
sdardis added a comment.
This revision is now accepted and ready to land.

LGTM with some nits (inlined).

The isCTI is only required for MIPSR6 instructions which cannot be placed in a forbidden slot. Since microMIPSR6 doesn't have forbidden slots and cannot be mixed inside MIPSR6 code without going through an ISA change it isn't required.


================
Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:3653
@@ -3652,3 +3652,3 @@
 unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
   // As described by the Mips32r2 spec, the registers Rd and Rs for
   // jalr.hb must be different.
----------------
Add a note here that it also applies to microMIPSR6.

================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:1020
@@ +1019,3 @@
+  bit hasDelaySlot = 0;
+  bit isCTI = 1;
+}
----------------
The 'isCTI' bit isn't required. The only code that cares about the 'isCTI' bit is the SafeInForbiddenSlot predicate which is only used for MIPSR6, not microMIPSR6.

================
Comment at: test/MC/Mips/micromips32r6/invalid.s:118
@@ +117,2 @@
+  jalrc.hb $31             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
+  jalrc.hb $31, $31        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
----------------
Add evp and dvp with immediate operands here to test that they are rejected.

================
Comment at: test/MC/Mips/micromips64r6/invalid.s:148
@@ +147,2 @@
+  jalrc.hb $31             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
+  jalrc.hb $31, $31        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
----------------
Here as well.


http://reviews.llvm.org/D18687