[PATCH] D18995: [mips] Fix emitAtomicCmpSwapPartword to handle 64 bit pointers correctly

[Zoran Jovanovic via llvm-commits]

zoran.jovanovic updated this revision to Diff 53524.
zoran.jovanovic added a comment.

New patch version that only changes type of AlignedAddr and uses appropriate AND instruction for calculating value of AlignedAddr  (although correct output will be produced with any AND instruction because they all work on register size data - functionally there is no AND32 and AND64).


http://reviews.llvm.org/D18995

Files:
  lib/Target/Mips/MipsISelLowering.cpp
  test/CodeGen/Mips/atomicCmpSwapPW.ll

Index: test/CodeGen/Mips/atomicCmpSwapPW.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Mips/atomicCmpSwapPW.ll
@@ -0,0 +1,11 @@
+; RUN: llc  -O0 -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s -filetype=asm -o - \
+; RUN:   | FileCheck %s
+
+; CHECK: ld $[[R0:[0-9]+]]
+; CHECK: ll ${{[0-9]+}}, 0($[[R0]])
+
+define {i16, i1} @foo(i16* %addr, i16 signext %r, i16 zeroext %new) {
+  %res = cmpxchg i16* %addr, i16 %r, i16 %new seq_cst seq_cst
+  ret {i16, i1} %res
+}
+
Index: lib/Target/Mips/MipsISelLowering.cpp
===================================================================
--- lib/Target/Mips/MipsISelLowering.cpp
+++ lib/Target/Mips/MipsISelLowering.cpp
@@ -1416,15 +1416,18 @@
   MachineFunction *MF = BB->getParent();
   MachineRegisterInfo &RegInfo = MF->getRegInfo();
   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
+  bool ArePtrs64bit = ABI.ArePtrs64bit();
+  const TargetRegisterClass *RCp =
+    getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
   DebugLoc DL = MI->getDebugLoc();
 
   unsigned Dest    = MI->getOperand(0).getReg();
   unsigned Ptr     = MI->getOperand(1).getReg();
   unsigned CmpVal  = MI->getOperand(2).getReg();
   unsigned NewVal  = MI->getOperand(3).getReg();
 
-  unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
+  unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
   unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
   unsigned Mask = RegInfo.createVirtualRegister(RC);
   unsigned Mask2 = RegInfo.createVirtualRegister(RC);
@@ -1482,7 +1485,7 @@
   int64_t MaskImm = (Size == 1) ? 255 : 65535;
   BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
     .addReg(Mips::ZERO).addImm(-4);
-  BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
+  BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
     .addReg(Ptr).addReg(MaskLSB2);
   BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
   if (Subtarget.isLittle()) {


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D18995.53524.patch
Type: text/x-patch
Size: 2060 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20160413/222ac3b7/attachment.bin>