[llvm] r266171 - [mips][microMIPS] Fix for "Cannot copy registers" assertion
Hrvoje Varga via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 12 23:17:22 PDT 2016
Author: hvarga
Date: Wed Apr 13 01:17:21 2016
New Revision: 266171
URL: http://llvm.org/viewvc/llvm-project?rev=266171&view=rev
Log:
[mips][microMIPS] Fix for "Cannot copy registers" assertion
Differential Revision: http://reviews.llvm.org/D17068
This changes contains fix for failing test-suite. So, this patch should hopefully work now.
Added:
llvm/trunk/test/CodeGen/Mips/cannot-copy-registers.ll
llvm/trunk/test/CodeGen/Mips/lw16-base-reg.ll
Modified:
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=266171&r1=266170&r2=266171&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Wed Apr 13 01:17:21 2016
@@ -49,7 +49,7 @@ def MicroMipsMemGPRMM16AsmOperand : AsmO
class mem_mm_4_generic : Operand<i32> {
let PrintMethod = "printMemOperand";
- let MIOperandInfo = (ops GPRMM16, simm4);
+ let MIOperandInfo = (ops ptr_rc, simm4);
let OperandType = "OPERAND_MEMORY";
let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
}
@@ -75,7 +75,7 @@ def MicroMipsMemSPAsmOperand : AsmOperan
def mem_mm_sp_imm5_lsl2 : Operand<i32> {
let PrintMethod = "printMemOperand";
- let MIOperandInfo = (ops GPR32:$base, simm5:$offset);
+ let MIOperandInfo = (ops ptr_rc:$base, simm5:$offset);
let OperandType = "OPERAND_MEMORY";
let ParserMatchClass = MicroMipsMemSPAsmOperand;
let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";
@@ -90,7 +90,7 @@ def mem_mm_gp_imm7_lsl2 : Operand<i32> {
def mem_mm_9 : Operand<i32> {
let PrintMethod = "printMemOperand";
- let MIOperandInfo = (ops GPR32, simm9);
+ let MIOperandInfo = (ops ptr_rc, simm9);
let EncoderMethod = "getMemEncodingMMImm9";
let ParserMatchClass = MipsMemSimm9AsmOperand;
let OperandType = "OPERAND_MEMORY";
@@ -98,7 +98,7 @@ def mem_mm_9 : Operand<i32> {
def mem_mm_12 : Operand<i32> {
let PrintMethod = "printMemOperand";
- let MIOperandInfo = (ops GPR32, simm12);
+ let MIOperandInfo = (ops ptr_rc, simm12);
let EncoderMethod = "getMemEncodingMMImm12";
let ParserMatchClass = MipsMemAsmOperand;
let OperandType = "OPERAND_MEMORY";
@@ -106,7 +106,7 @@ def mem_mm_12 : Operand<i32> {
def mem_mm_16 : Operand<i32> {
let PrintMethod = "printMemOperand";
- let MIOperandInfo = (ops GPR32, simm16);
+ let MIOperandInfo = (ops ptr_rc, simm16);
let EncoderMethod = "getMemEncodingMMImm16";
let ParserMatchClass = MipsMemAsmOperand;
let OperandType = "OPERAND_MEMORY";
@@ -122,7 +122,7 @@ def MipsMemUimm4AsmOperand : AsmOperandC
def mem_mm_4sp : Operand<i32> {
let PrintMethod = "printMemOperand";
- let MIOperandInfo = (ops GPR32, uimm8);
+ let MIOperandInfo = (ops ptr_rc, uimm8);
let EncoderMethod = "getMemEncodingMMImm4sp";
let ParserMatchClass = MipsMemUimm4AsmOperand;
let OperandType = "OPERAND_MEMORY";
@@ -203,7 +203,7 @@ def movep_regpair : Operand<i32> {
let ParserMatchClass = MovePRegPairAsmOperand;
let PrintMethod = "printRegisterList";
let DecoderMethod = "DecodeMovePRegPair";
- let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
+ let MIOperandInfo = (ops ptr_rc, ptr_rc);
}
class MovePMM16<string opstr, RegisterOperand RO> :
@@ -224,7 +224,7 @@ def regpair : Operand<i32> {
let ParserMatchClass = RegPairAsmOperand;
let PrintMethod = "printRegisterPair";
let DecoderMethod = "DecodeRegPairOperand";
- let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
+ let MIOperandInfo = (ops ptr_rc, ptr_rc);
}
class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
Modified: llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp?rev=266171&r1=266170&r2=266171&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp Wed Apr 13 01:17:21 2016
@@ -42,7 +42,9 @@ unsigned MipsFunctionInfo::getGlobalBase
STI.inMips16Mode()
? &Mips::CPU16RegsRegClass
: STI.inMicroMipsMode()
- ? &Mips::GPRMM16RegClass
+ ? STI.hasMips64()
+ ? &Mips::GPRMM16_64RegClass
+ : &Mips::GPRMM16RegClass
: static_cast<const MipsTargetMachine &>(MF.getTarget())
.getABI()
.IsN64()
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=266171&r1=266170&r2=266171&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Wed Apr 13 01:17:21 2016
@@ -51,7 +51,13 @@ const TargetRegisterClass *
MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
unsigned Kind) const {
MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
- return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
+ bool inMicroMips = MF.getSubtarget<MipsSubtarget>().inMicroMipsMode();
+
+ return ABI.ArePtrs64bit() ?
+ inMicroMips ?
+ &Mips::GPRMM16_64RegClass : &Mips::GPR64RegClass
+ : inMicroMips ?
+ &Mips::GPRMM16RegClass : &Mips::GPR32RegClass;
}
unsigned
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=266171&r1=266170&r2=266171&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Wed Apr 13 01:17:21 2016
@@ -330,6 +330,12 @@ def GPR64 : RegisterClass<"Mips", [i64],
// Reserved
K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>;
+def GPRMM16_64 : RegisterClass<"Mips", [i64], 64, (add
+ // Callee save
+ S0_64, S1_64,
+ // Return Values and Arguments
+ V0_64, V1_64, A0_64, A1_64, A2_64, A3_64)>;
+
def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
// Return Values and Arguments
V0, V1, A0, A1, A2, A3,
Added: llvm/trunk/test/CodeGen/Mips/cannot-copy-registers.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cannot-copy-registers.ll?rev=266171&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cannot-copy-registers.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/cannot-copy-registers.ll Wed Apr 13 01:17:21 2016
@@ -0,0 +1,24 @@
+; RUN: llc -march=mips64 -mcpu=mips64r6 -mattr=+micromips \
+; RUN: -relocation-model=pic -O3 < %s
+
+; Check that message "Cannot copy registers" is not asserted in case of microMIPS64r6.
+
+ at x = global i32 65504, align 4
+ at y = global i32 60929, align 4
+ at .str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1
+
+define i32 @main() nounwind {
+entry:
+ %0 = load i32, i32* @x, align 4
+ %and1 = and i32 %0, 4
+ %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds
+ ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %and1)
+
+ %1 = load i32, i32* @y, align 4
+ %and2 = and i32 %1, 5
+ %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds
+ ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %and2)
+ ret i32 0
+}
+
+declare i32 @printf(i8*, ...)
Added: llvm/trunk/test/CodeGen/Mips/lw16-base-reg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/lw16-base-reg.ll?rev=266171&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/lw16-base-reg.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/lw16-base-reg.ll Wed Apr 13 01:17:21 2016
@@ -0,0 +1,26 @@
+; RUN: llc %s -march=mips -mcpu=mips32r3 -mattr=micromips -filetype=asm \
+; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
+; RUN: llc %s -march=mips64 -mcpu=mips64r3 -mattr=micromips -filetype=asm \
+; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
+
+; The purpose of this test is to check whether the CodeGen selects
+; LW16 instruction with the base register in a range of $2-$7, $16, $17.
+
+%struct.T = type { i32 }
+
+$_ZN1TaSERKS_ = comdat any
+
+define linkonce_odr void @_ZN1TaSERKS_(%struct.T* %this, %struct.T* dereferenceable(4) %t) #0 comdat align 2 {
+entry:
+ %this.addr = alloca %struct.T*, align 4
+ %t.addr = alloca %struct.T*, align 4
+ %this1 = load %struct.T*, %struct.T** %this.addr, align 4
+ %0 = load %struct.T*, %struct.T** %t.addr, align 4
+ %V3 = getelementptr inbounds %struct.T, %struct.T* %0, i32 0, i32 0
+ %1 = load i32, i32* %V3, align 4
+ %V4 = getelementptr inbounds %struct.T, %struct.T* %this1, i32 0, i32 0
+ store i32 %1, i32* %V4, align 4
+ ret void
+}
+
+; CHECK: lw16 ${{[0-9]+}}, 0(${{[2-7]|16|17}})
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