[PATCH] D19021: AMDGPU/SI: Fix spilling of 96-bit registers

[Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL266152: AMDGPU/SI: Fix spilling of 96-bit registers (authored by tstellar).

Changed prior to commit:
  http://reviews.llvm.org/D19021?vs=53424&id=53496#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D19021

Files:
  llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp

Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -551,6 +551,8 @@
     return AMDGPU::SI_SPILL_V32_SAVE;
   case 8:
     return AMDGPU::SI_SPILL_V64_SAVE;
+  case 12:
+    return AMDGPU::SI_SPILL_V96_SAVE;
   case 16:
     return AMDGPU::SI_SPILL_V128_SAVE;
   case 32:
@@ -642,6 +644,8 @@
     return AMDGPU::SI_SPILL_V32_RESTORE;
   case 8:
     return AMDGPU::SI_SPILL_V64_RESTORE;
+  case 12:
+    return AMDGPU::SI_SPILL_V96_RESTORE;
   case 16:
     return AMDGPU::SI_SPILL_V128_RESTORE;
   case 32:


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