[llvm] r266144 - [AArch64] Fuse AES{D,E}/AESMC for Exynos M1. (NFC)

[Evandro Menezes via llvm-commits]

Author: evandro
Date: Tue Apr 12 17:42:36 2016
New Revision: 266144

URL: http://llvm.org/viewvc/llvm-project?rev=266144&view=rev
Log:
[AArch64] Fuse AES{D,E}/AESMC for Exynos M1. (NFC)

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td?rev=266144&r1=266143&r2=266144&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td Tue Apr 12 17:42:36 2016
@@ -347,7 +347,10 @@ def : InstRW<[M1WriteNALU1],  (instregex
 // ASIMD store instructions.
 
 // Cryptography instructions.
-def : InstRW<[M1WriteNCRYPT1], (instregex "^AES")>;
+def M1WriteAES : SchedWriteRes<[M1UnitNCRYPT]> { let Latency = 1; }
+def M1ReadAES  : SchedReadAdvance<1, [M1WriteAES]>;
+def : InstRW<[M1WriteAES, M1ReadAES], (instregex "^AES")>;
+
 def : InstRW<[M1WriteNCRYPT1], (instregex "^PMUL")>;
 def : InstRW<[M1WriteNCRYPT1], (instregex "^SHA1(H|SU)")>;
 def : InstRW<[M1WriteNCRYPT5], (instregex "^SHA1[CMP]")>;