[PATCH] D19005: CodeGen, AArch64, ARM, X86: Simplify SplitCSR

[Manman Ren via llvm-commits]

manmanren added a comment.

Some general comments:
Is this NFC (no functionality change)? I noticed a small testing case change.

I think the original code tries to make it easy for a target to start supporting splitCSR, or for a calling convention to start using splitCSR.
With this updated approach, is it still easy to do so? I didn't really look through the patch to figure out how :]

Cheers,
Manman


================
Comment at: include/llvm/Target/TargetLowering.h:2670
@@ +2669,3 @@
+  /// Note: Typically used to add operands to the target return instruction when
+  /// some callee saved registers are kepy in vregs because they are also used
+  /// for function parameters.
----------------
typo: kepy

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:2678
@@ +2677,3 @@
+      MF.getFunction()->hasFnAttribute(Attribute::NoUnwind) &&
+      !MF.getTarget().Options.EnableFastISel && mayUseSplitCSR(MF)) {
+    const MCPhysReg *SavedViaCopy =
----------------
I don't quite like this getting duplicated in every target that supports SplitCSR and in the already heavy LowerFormalArguments. Can we wrap this up somehow?

If we want to support another Calling convention, we will have more conditions here.


Repository:
  rL LLVM

http://reviews.llvm.org/D19005