[llvm] r262627 - [X86] Don't assume that shuffle non-mask operands starts at #0.

[Ahmed Bougacha via llvm-commits]

Tom, Nadav: I'd like to get this into 3.8.1.  The branch had already
diverged quite a bit, so attached is a minimal patch, containing:

- the relevant parts of this commit
- r260315 [X86] Don't reuse an unrelated variable, create a new one. NFC.
- the VPSHUFB lane-crossing check of r260063 [X86][SSE] Resolve target
shuffle inputs to sentinels to permit more combines

This fixes PR27320.

-Ahmed


On Thu, Mar 3, 2016 at 8:53 AM, Ahmed Bougacha via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: ab
> Date: Thu Mar  3 10:53:50 2016
> New Revision: 262627
>
> URL: http://llvm.org/viewvc/llvm-project?rev=262627&view=rev
> Log:
> [X86] Don't assume that shuffle non-mask operands starts at #0.
>
> That's not the case for VPERMV/VPERMV3, which cover all possible
> combinations (the C intrinsics use a different order; the AVX vs
> AVX512 intrinsics are different still).
>
> Since:
>   r246981 AVX-512: Lowering for 512-bit vector shuffles.
> VPERMV is recognized in getTargetShuffleMask.
>
> This breaks assumptions in most callers, as they expect
> the non-mask operands to start at index 0.
> VPERMV has the mask as operand #0; VPERMV3 has it in the middle.
>
> Instead of the faulty assumption, have getTargetShuffleMask return
> its operands as well.
>
> One alternative we considered was to change the operand order of
> VPERMV, but we agreed to stick to the instruction order, as there
> are more AVX512 weirdness to cover (vpermt2/vpermi2 in particular).
>
> Differential Revision: http://reviews.llvm.org/D17041
>
> Added:
>     llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
> Modified:
>     llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>     llvm/trunk/lib/Target/X86/X86ISelLowering.h
>
>
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