[llvm] r266028 - [AArch64] Add a test case for the propagation of register banks through

[Quentin Colombet via llvm-commits]

Author: qcolombet
Date: Mon Apr 11 19:32:55 2016
New Revision: 266028

URL: http://llvm.org/viewvc/llvm-project?rev=266028&view=rev
Log:
[AArch64] Add a test case for the propagation of register banks through
phis.

Modified:
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir?rev=266028&r1=266027&r2=266028&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir Mon Apr 11 19:32:55 2016
@@ -25,6 +25,18 @@
   entry:
     ret void
   }
+  define void @phiPropagation(i32* %src, i32* %dst, i1 %cond) {
+  entry:
+    %srcVal = load i32, i32* %src
+    br i1 %cond, label %end, label %then
+  then:
+    %res = add i32 %srcVal, 36
+    br label %end
+  end:
+    %toStore = phi i32 [ %srcVal, %entry ], [ %res, %then ]
+    store i32 %toStore, i32* %dst
+    ret void
+  }
 ...
 
 ---
@@ -128,3 +140,40 @@ body: |
     %0(32) = COPY %w0
     %1(32) = G_ADD i32 %0, %w0
 ...
+
+---
+# Check that we are able to propagate register banks from phis.
+name:            phiPropagation
+isSSA:           true
+tracksRegLiveness:   true
+# CHECK:      registers:
+# CHECK-NEXT:   - { id: 0, class: gpr32 }
+# CHECK-NEXT:   - { id: 1, class: gpr64sp }
+# CHECK-NEXT:   - { id: 2, class: gpr32 }
+# CHECK-NEXT:   - { id: 3, class: gpr }
+# CHECK-NEXT:   - { id: 4, class: gpr }
+registers:
+  - { id: 0, class: gpr32 }
+  - { id: 1, class: gpr64sp }
+  - { id: 2, class: gpr32 }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body: |
+  bb.0.entry:
+    successors: %bb.2.end, %bb.1.then
+    liveins: %x0, %x1, %w2
+  
+    %0 = LDRWui killed %x0, 0 :: (load 4 from %ir.src)
+    %1 = COPY %x1
+    %2 = COPY %w2
+    TBNZW killed %2, 0, %bb.2.end
+  
+  bb.1.then:
+    successors: %bb.2.end
+    %3(32) = G_ADD i32 %0, %0
+  
+  bb.2.end:
+    %4(32) = PHI %0, %bb.0.entry, %3, %bb.1.then
+    STRWui killed %4, killed %1, 0 :: (store 4 into %ir.dst)
+    RET_ReallyLR
+...