[llvm] r266026 - [AArch64] Add a test case for the repairing of definitions.

[Quentin Colombet via llvm-commits]

Author: qcolombet
Date: Mon Apr 11 19:25:22 2016
New Revision: 266026

URL: http://llvm.org/viewvc/llvm-project?rev=266026&view=rev
Log:
[AArch64] Add a test case for the repairing of definitions.

Modified:
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir?rev=266026&r1=266025&r2=266026&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir Mon Apr 11 19:25:22 2016
@@ -21,6 +21,10 @@
   entry:
     ret void
   }
+  define void @defaultMappingDefRepair() {
+  entry:
+    ret void
+  }
 ...
 
 ---
@@ -100,3 +104,27 @@ body: |
     %0(32) = COPY %s0
     %1(32) = G_ADD i32 %0, %0
 ...
+
+---
+# Check that we repair the definition of %1.
+# %1 is forced to be into FPR, but its definition actually
+# requires that it lives in GPR. Make sure regbankselect
+# fixes that.
+name:            defaultMappingDefRepair
+isSSA:           true
+# CHECK:      registers:
+# CHECK-NEXT:   - { id: 0, class: gpr }
+# CHECK-NEXT:   - { id: 1, class: fpr }
+# CHECK-NEXT:   - { id: 2, class: gpr }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: fpr }
+body: |
+  bb.0.entry:
+    liveins: %w0
+    ; CHECK:           %0(32) = COPY %w0
+    ; CHECK-NEXT:      %2(32) = G_ADD i32 %0, %w0
+    ; CHECK-NEXT:      %1(32) = COPY %2
+    %0(32) = COPY %w0
+    %1(32) = G_ADD i32 %0, %w0
+...