[llvm] r266021 - [AArch64] Test that RegBankSelect inserts the proper copies to fix the

[Quentin Colombet via llvm-commits]

Author: qcolombet
Date: Mon Apr 11 19:00:42 2016
New Revision: 266021

URL: http://llvm.org/viewvc/llvm-project?rev=266021&view=rev
Log:
[AArch64] Test that RegBankSelect inserts the proper copies to fix the
register bank assignments.

Modified:
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir?rev=266021&r1=266020&r2=266021&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir Mon Apr 11 19:00:42 2016
@@ -13,6 +13,14 @@
   entry:
     ret void
   }
+  define void @defaultMapping1Repair() {
+  entry:
+    ret void
+  }
+  define void @defaultMapping2Repairs() {
+  entry:
+    ret void
+  }
 ...
 
 ---
@@ -47,3 +55,48 @@ body: |
     ; CHECK:      %0(32) = G_ADD <2 x i32> %d0
     %0(32) = G_ADD <2 x i32> %d0, %d0
 ...
+
+---
+# Check that we repair the assignment for %0.
+# Indeed based on the source of the copy it should live
+# in FPR, but at the use, it should be GPR.
+name:            defaultMapping1Repair
+isSSA:           true
+# CHECK:      registers:
+# CHECK-NEXT:   - { id: 0, class: fpr }
+# CHECK-NEXT:   - { id: 1, class: gpr }
+# CHECK-NEXT:   - { id: 2, class: gpr }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body: |
+  bb.0.entry:
+    liveins: %s0, %x0
+    ; CHECK:           %0(32) = COPY %s0
+    ; CHECK-NEXT:      %2(32) = COPY %0
+    ; CHECK-NEXT:      %1(32) = G_ADD i32 %2, %x0
+    %0(32) = COPY %s0
+    %1(32) = G_ADD i32 %0, %x0
+...
+
+# Check that we repair the assignment for %0 differently for both uses.
+name:            defaultMapping2Repairs
+isSSA:           true
+# CHECK:      registers:
+# CHECK-NEXT:   - { id: 0, class: fpr }
+# CHECK-NEXT:   - { id: 1, class: gpr }
+# CHECK-NEXT:   - { id: 2, class: gpr }
+# CHECK-NEXT:   - { id: 3, class: gpr }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body: |
+  bb.0.entry:
+    liveins: %s0, %x0
+    ; CHECK:           %0(32) = COPY %s0
+    ; CHECK-NEXT:      %2(32) = COPY %0
+    ; CHECK-NEXT:      %3(32) = COPY %0
+    ; CHECK-NEXT:      %1(32) = G_ADD i32 %2, %3
+    %0(32) = COPY %s0
+    %1(32) = G_ADD i32 %0, %0
+...