[PATCH] D18996: [PPC] Enable shuffling of VSX vectors
Guozhi Wei via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 11 15:42:49 PDT 2016
Carrot created this revision.
Carrot added a reviewer: hfinkel.
Carrot added a subscriber: llvm-commits.
Current PPC backend enables shuffling for very limited vector types, and the default behavior for a vector with more than 2 elements is moving data through memory, it usually triggers store forwarding, it is extremely slow on power.
This simple patch explicitly enables shuffling of vectors if VSX is available. For the testcase in the bug entry, the performance is improved by 6.6x on power8. The number of instructions is reduced from 756 to 406.
http://reviews.llvm.org/D18996
Files:
lib/Target/PowerPC/PPCISelLowering.cpp
test/CodeGen/PowerPC/pr27078.ll
Index: test/CodeGen/PowerPC/pr27078.ll
===================================================================
--- test/CodeGen/PowerPC/pr27078.ll
+++ test/CodeGen/PowerPC/pr27078.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=+vsx < %s | FileCheck %s
+
+define <4 x float> @bar(float* %p, float* %q) {
+ %1 = bitcast float* %p to <12 x float>*
+ %2 = bitcast float* %q to <12 x float>*
+ %3 = load <12 x float>, <12 x float>* %1, align 16
+ %4 = load <12 x float>, <12 x float>* %2, align 16
+ %5 = fsub <12 x float> %4, %3
+ %6 = shufflevector <12 x float> %5, <12 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
+ ret <4 x float> %6
+
+; CHECK: vspltw
+; CHECK: vmrghw
+; CHECK: vsldoi
+}
Index: lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelLowering.cpp
+++ lib/Target/PowerPC/PPCISelLowering.cpp
@@ -11925,6 +11925,9 @@
return true;
}
+ if (Subtarget.hasVSX())
+ return true;
+
return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
}
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