[PATCH] D18952: [SystemZ] Add SVC instruction.

[Ulrich Weigand via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL265943: [SystemZ] Add SVC instruction (authored by uweigand).

Changed prior to commit:
  http://reviews.llvm.org/D18952?vs=53240&id=53245#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D18952

Files:
  llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
  llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
  llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
  llvm/trunk/test/MC/SystemZ/insn-good.s

Index: llvm/trunk/test/MC/SystemZ/insn-good.s
===================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good.s
+++ llvm/trunk/test/MC/SystemZ/insn-good.s
@@ -8973,6 +8973,16 @@
 	strvg	%r0,524287(%r15,%r1)
 	strvg	%r15,0
 
+#CHECK: svc	0			# encoding: [0x0a,0x00]
+#CHECK: svc	3			# encoding: [0x0a,0x03]
+#CHECK: svc	128			# encoding: [0x0a,0x80]
+#CHECK: svc	255			# encoding: [0x0a,0xff]
+
+	svc	0
+	svc	3
+	svc	128
+	svc	0xff
+
 #CHECK: sty	%r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x50]
 #CHECK: sty	%r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x50]
 #CHECK: sty	%r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x50]
Index: llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
@@ -8698,6 +8698,18 @@
 # CHECK: sty %r15, 0
 0xe3 0xf0 0x00 0x00 0x00 0x50
 
+# CHECK: svc 0
+0x0a 0x00
+
+# CHECK: svc 3
+0x0a 0x03
+
+# CHECK: svc 128
+0x0a 0x80
+
+# CHECK: svc 255
+0x0a 0xff
+
 # CHECK: sxbr %f0, %f0
 0xb3 0x4b 0x00 0x00
 
Index: llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
===================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -158,6 +158,17 @@
 //
 //===----------------------------------------------------------------------===//
 
+class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstSystemZ<2, outs, ins, asmstr, pattern> {
+  field bits<16> Inst;
+  field bits<16> SoftFail = 0;
+
+  bits<8> I1;
+
+  let Inst{15-8} = op;
+  let Inst{7-0}  = I1;
+}
+
 class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
Index: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -1570,6 +1570,10 @@
   defm SRST : StringRRE<"srst", 0xb25e, z_search_string>;
 
 // Other instructions for inline assembly
+let hasSideEffects = 1, Defs = [CC], isCall = 1 in
+  def SVC : InstI<0x0A, (outs), (ins imm32zx8:$I1),
+                  "svc\t$I1",
+                  []>;
 let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
   def STCK : InstS<0xB205, (outs), (ins bdaddr12only:$BD2),
                        "stck\t$BD2",


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