[PATCH] D18941: Use the correct scratch wave offset register for shaders.

[Bas Nieuwenhuizen via llvm-commits]

bnieuwenhuizen created this revision.
bnieuwenhuizen added reviewers: tstellarAMD, arsenm, mareko, nhaehnle.
bnieuwenhuizen added a subscriber: llvm-commits.
Herald added subscribers: arsenm, qcolombet.

The code previously always used s1 as it was using the user + system SGPR
information for compute kernels. This is incorrect for Mesa shaders though,

The register should be the next SGPR after all user and system SGPR's.
We use that Mesa adds arguments for all input and system SGPR's and
take the next available SGPR for the scratch wave offset register.

Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

http://reviews.llvm.org/D18941

Files:
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
  lib/Target/AMDGPU/SIMachineFunctionInfo.h
  test/CodeGen/AMDGPU/large-alloca-graphics.ll
  test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll

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