[PATCH] D18850: [X86]: Fix for PR27251

[Simon Pilgrim via llvm-commits]

RKSimon added a subscriber: RKSimon.
RKSimon added a comment.

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> > Comment at: test/CodeGen/X86/vector-blend.ll:1011

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> > @@ -1010,3 +1010,3 @@

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> >  ; SSE2-NEXT:    pslld $31, %xmm1

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> >  ; SSE2-NEXT:    psrad $31, %xmm1

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> > ; SSE2-NEXT:    pxor %xmm1, %xmm0

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> > ---------------------------------

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> > I know this isn't related to your change, but the redundant shifts here are

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> > pretty gross.

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> Why are the shifts redundant?  One is a shift left by 31, and the other is a arithmetic shift right by 31.

>  This has the effect of propagating bit 0 through all 32 bits of the vector element.


For the pre-SSE41 cases its doing ashr( shl( lshr( v, 31 ), 31 ), 31) which should be combined to ashr( v, 31 ) - this isn't that difficult.

For the SSE41 cases we don't need the shifts at all as (v)blendvps will select elements based on the sign bit alone, but the vselect/blendv relationship is rather nasty (change in input type behaviour after legalization) and I can imagine a number of problems getting it to work cleanly - I've hit some of these before trying to do late constant folding of vselect.


Repository:
  rL LLVM

http://reviews.llvm.org/D18850