[PATCH] D18602: AMDGPU/SI: Enable the post-ra scheduler

[Tom Stellard via llvm-commits]

tstellarAMD updated this revision to Diff 52937.
tstellarAMD added a comment.

Use MI->modifiesRegister instead of definesRegister.  Also move most of
the EmitInstruction() code into AdvanceCycle() which better matches
how the hazard recognizer is used by the scheduler.


http://reviews.llvm.org/D18602

Files:
  lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  lib/Target/AMDGPU/CMakeLists.txt
  lib/Target/AMDGPU/GCNHazardRecognizer.cpp
  lib/Target/AMDGPU/GCNHazardRecognizer.h
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.h
  lib/Target/AMDGPU/SIRegisterInfo.cpp
  lib/Target/AMDGPU/SIRegisterInfo.h
  lib/Target/AMDGPU/SISchedule.td
  test/CodeGen/AMDGPU/fract.f64.ll
  test/CodeGen/AMDGPU/half.ll
  test/CodeGen/AMDGPU/insert_vector_elt.ll
  test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll
  test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.clamped.f64.ll
  test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.clamped.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll
  test/CodeGen/AMDGPU/llvm.round.ll
  test/CodeGen/AMDGPU/mad-combine.ll
  test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll
  test/CodeGen/AMDGPU/setcc-opt.ll
  test/CodeGen/AMDGPU/shift-i64-opts.ll
  test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll
  test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
  test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
  test/CodeGen/AMDGPU/trunc.ll
  test/CodeGen/AMDGPU/uniform-cfg.ll
  test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
  test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll

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