[llvm] r265678 - AMDGPU/SI: Add MachineBasicBlock parameter to SIInstrInfo::insertWaitStates
Tom Stellard via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 7 07:47:07 PDT 2016
Author: tstellar
Date: Thu Apr 7 09:47:07 2016
New Revision: 265678
URL: http://llvm.org/viewvc/llvm-project?rev=265678&view=rev
Log:
AMDGPU/SI: Add MachineBasicBlock parameter to SIInstrInfo::insertWaitStates
Summary: This makes it possible to insert nops at the end of blocks.
Reviewers: arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D18549
Modified:
llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp?rev=265678&r1=265677&r2=265678&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp Thu Apr 7 09:47:07 2016
@@ -519,7 +519,7 @@ void SIInsertWaits::insertDPPWaitStates(
continue;
if (DPP->readsRegister(Op.getReg(), TRI)) {
- TII->insertWaitStates(DPP, WaitStates);
+ TII->insertWaitStates(*DPP->getParent(), DPP, WaitStates);
return;
}
}
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=265678&r1=265677&r2=265678&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Thu Apr 7 09:47:07 2016
@@ -801,7 +801,8 @@ unsigned SIInstrInfo::calculateLDSSpillA
return TmpReg;
}
-void SIInstrInfo::insertWaitStates(MachineBasicBlock::iterator MI,
+void SIInstrInfo::insertWaitStates(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
int Count) const {
while (Count > 0) {
int Arg;
@@ -810,7 +811,7 @@ void SIInstrInfo::insertWaitStates(Machi
else
Arg = Count - 1;
Count -= 8;
- BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
+ BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
.addImm(Arg);
}
}
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h?rev=265678&r1=265677&r2=265678&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h Thu Apr 7 09:47:07 2016
@@ -437,7 +437,8 @@ public:
void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
unsigned SavReg, unsigned IndexReg) const;
- void insertWaitStates(MachineBasicBlock::iterator MI, int Count) const;
+ void insertWaitStates(MachineBasicBlock &MBB,MachineBasicBlock::iterator MI,
+ int Count) const;
/// \brief Returns the operand named \p Op. If \p MI does not have an
/// operand named \c Op, this function returns nullptr.
Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=265678&r1=265677&r2=265678&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp Thu Apr 7 09:47:07 2016
@@ -414,7 +414,7 @@ void SIRegisterInfo::eliminateFrameIndex
case AMDGPUSubtarget::SOUTHERN_ISLANDS:
// "VALU writes SGPR" -> "SMRD reads that SGPR" needs 4 wait states
// ("S_NOP 3") on SI
- TII->insertWaitStates(MI, 4);
+ TII->insertWaitStates(*MBB, MI, 4);
break;
case AMDGPUSubtarget::SEA_ISLANDS:
break;
@@ -422,7 +422,7 @@ void SIRegisterInfo::eliminateFrameIndex
// "VALU writes SGPR -> VMEM reads that SGPR" needs 5 wait states
// ("S_NOP 4") on VI and later. This also applies to VALUs which write
// VCC, but we're unlikely to see VMEM use VCC.
- TII->insertWaitStates(MI, 5);
+ TII->insertWaitStates(*MBB, MI, 5);
}
MI->eraseFromParent();
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